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    <title>topic Scatter the processes across sockets in Intel® MPI Library</title>
    <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1610143#M11767</link>
    <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I am researching how to pin processes across sockets using the &lt;/SPAN&gt;I_MPI_PIN_DOMAIN&lt;SPAN&gt; and &lt;/SPAN&gt;I_MPI_PIN_ORDER&lt;SPAN&gt; environment variables. I have tried many combinations, but none of them have worked. I used Intel MPI 2021.12.1 and ran &lt;A href="https://github.com/TACC/amask" target="_self"&gt;TACC&amp;nbsp;&lt;/A&gt;&lt;/SPAN&gt;&lt;A href="https://github.com/TACC/amask" target="_self"&gt;amask&lt;/A&gt;&lt;SPAN&gt; on two systems: one equipped with two Xeon Platinum 8470 CPUs and the other equipped with two Xeon CPU Max 9470 CPUs.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;With the default settings, I ran the following command:&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;PRE&gt;mpiexec -n 4 amask_mpi&lt;/PRE&gt;&lt;P&gt;and I got the process placement in bunch order as expected:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Each row of matrix is a mask for a Hardware Thread (hwt).&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;CORE ID&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= matrix digit + column group # in |...|&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;A set mask bit (proc-id) = core id + add 104 to each additional row. &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;rank |&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;0&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;10&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;20&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;30&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;40&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;50&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;60&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;70&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;80&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;90&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;100 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0000 0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2-----------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0001 --2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0002 -1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3----------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0003 ---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5--------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/PRE&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;The first two processes are bound to the first and second NUMA nodes in the first socket, and the remaining two processes are bound to the first and second NUMA nodes in the second socket.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can also achieve the process placement in compact order with the following variables:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;I_MPI_PIN_DOMAIN = core&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;I_MPI_PIN_ORDER = compact&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;and I got the processes placed in the first NUMA node:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Each row of matrix is a mask for a Hardware Thread (hwt). &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;CORE ID&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= matrix digit + column group # in |...| &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;A set mask bit (proc-id) = core id + add 104 to each additional row.&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;rank |&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;0&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;10&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;20&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;30&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;40&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;50&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;60&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;70&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;80&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;90&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;100 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0000 0-------------------------------------------------------------------------------------------------------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0001 --------8-----------------------------------------------------------------------------------------------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0002 ----------------6---------------------------------------------------------------------------------------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0003 ------------------------4------------------------------------------------------------------------------- &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I have been experimenting with different values of I_MPI_PIN_DOMAIN&lt;SPAN&gt; and &lt;/SPAN&gt;I_MPI_PIN_ORDER to achieve process placement in a scatter order across sockets. For example, I want the first and third processes to be bound to the first socket, and the second and fourth processes to be bound to the second socket. However, I have not had any success in finding a working combination. Could you please provide any suggestions? Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 27 Jun 2024 00:10:59 GMT</pubDate>
    <dc:creator>ZQyouOSC</dc:creator>
    <dc:date>2024-06-27T00:10:59Z</dc:date>
    <item>
      <title>Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1610143#M11767</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I am researching how to pin processes across sockets using the &lt;/SPAN&gt;I_MPI_PIN_DOMAIN&lt;SPAN&gt; and &lt;/SPAN&gt;I_MPI_PIN_ORDER&lt;SPAN&gt; environment variables. I have tried many combinations, but none of them have worked. I used Intel MPI 2021.12.1 and ran &lt;A href="https://github.com/TACC/amask" target="_self"&gt;TACC&amp;nbsp;&lt;/A&gt;&lt;/SPAN&gt;&lt;A href="https://github.com/TACC/amask" target="_self"&gt;amask&lt;/A&gt;&lt;SPAN&gt; on two systems: one equipped with two Xeon Platinum 8470 CPUs and the other equipped with two Xeon CPU Max 9470 CPUs.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;With the default settings, I ran the following command:&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;PRE&gt;mpiexec -n 4 amask_mpi&lt;/PRE&gt;&lt;P&gt;and I got the process placement in bunch order as expected:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Each row of matrix is a mask for a Hardware Thread (hwt).&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;CORE ID&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= matrix digit + column group # in |...|&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;A set mask bit (proc-id) = core id + add 104 to each additional row. &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;rank |&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;0&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;10&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;20&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;30&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;40&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;50&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;60&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;70&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;80&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;90&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;100 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0000 0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2-----------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0001 --2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---8---2---6---0---4---------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0002 -1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3----------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0003 ---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5---9---3---7---1---5--------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/PRE&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;The first two processes are bound to the first and second NUMA nodes in the first socket, and the remaining two processes are bound to the first and second NUMA nodes in the second socket.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can also achieve the process placement in compact order with the following variables:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;I_MPI_PIN_DOMAIN = core&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;I_MPI_PIN_ORDER = compact&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;and I got the processes placed in the first NUMA node:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Each row of matrix is a mask for a Hardware Thread (hwt). &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;CORE ID&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= matrix digit + column group # in |...| &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;A set mask bit (proc-id) = core id + add 104 to each additional row.&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;rank |&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;0&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;10&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;20&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;30&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;40&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;50&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;60&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;70&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;80&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;90&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;100 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0000 0-------------------------------------------------------------------------------------------------------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0001 --------8-----------------------------------------------------------------------------------------------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0002 ----------------6---------------------------------------------------------------------------------------&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0003 ------------------------4------------------------------------------------------------------------------- &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I have been experimenting with different values of I_MPI_PIN_DOMAIN&lt;SPAN&gt; and &lt;/SPAN&gt;I_MPI_PIN_ORDER to achieve process placement in a scatter order across sockets. For example, I want the first and third processes to be bound to the first socket, and the second and fourth processes to be bound to the second socket. However, I have not had any success in finding a working combination. Could you please provide any suggestions? Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 27 Jun 2024 00:10:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1610143#M11767</guid>
      <dc:creator>ZQyouOSC</dc:creator>
      <dc:date>2024-06-27T00:10:59Z</dc:date>
    </item>
    <item>
      <title>Re: Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611229#M11777</link>
      <description>&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/365617"&gt;@ZQyouOSC&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Can you please post the output after setting export I_MPI_DEBUG=10 ?&lt;/P&gt;</description>
      <pubDate>Mon, 01 Jul 2024 16:35:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611229#M11777</guid>
      <dc:creator>TobiasK</dc:creator>
      <dc:date>2024-07-01T16:35:37Z</dc:date>
    </item>
    <item>
      <title>Re: Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611893#M11782</link>
      <description>&lt;P&gt;Sure. The following is the output with&amp;nbsp;&lt;SPAN&gt;I_MPI_DEBUG=10,&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;I_MPI_PIN_DOMAIN=core and&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;I_MPI_PIN_ORDER=scatter:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Intel(R) MPI Library, Version 2021.10&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;Build 20230619 (id: c2e19c2f3e)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Copyright (C) 2003-2023 Intel Corporation.&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;All rights reserved.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[&lt;/SPAN&gt;&lt;SPAN class=""&gt;0&lt;/SPAN&gt;&lt;SPAN class=""&gt;]&lt;/SPAN&gt;&lt;SPAN class=""&gt; MPI startup(): library kind: release&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): shm segment size (342 MB per rank) * (4 local ranks) = 1368 MB total&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): libfabric loaded: libfabric.so.1 &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): libfabric version: 1.18.0-impi&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): max number of MPI_Request per vci: 67108864 (pools: 1)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): libfabric provider: mlx &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): File "/apps/spack/0.21/cardinal/linux-rhel9-sapphirerapids/intel-oneapi-mpi/intel/2021.10.0/2021.10.0-a2ei2t4/mpi/2021.10.0/etc/tuning_spr_shm-ofi_mlx_100.dat" not found&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Load tuning file: "/apps/spack/0.21/cardinal/linux-rhel9-sapphirerapids/intel-oneapi-mpi/intel/2021.10.0/2021.10.0-a2ei2t4/mpi/2021.10.0/etc/tuning_spr_shm-ofi.dat"&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: mode: direct&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: vcis: 1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: app_threads: -1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: runtime: generic&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: progress_threads: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: async_progress: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: lock_level: global&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): tag bits available: 20 (TAG_UB value: 1048575) &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): source bits available: 21 (Maximal number of rank: 2097151) &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Rank&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Pid&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Node name&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Pin cpu &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 0 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;776163 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{0} &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 1 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;776164 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{8} &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 2 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;776165 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{16}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 3 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;776166 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{24}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_CC=icc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_CXX=icpc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_FC=ifort&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_F90=ifort&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_F77=ifort&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_ROOT=/apps/spack/0.21/cardinal/linux-rhel9-sapphirerapids/intel-oneapi-mpi/intel/2021.10.0/2021.10.0-a2ei2t4/mpi/2021.10.0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_BIND_WIN_ALLOCATE=localalloc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_BOOTSTRAP_EXEC_EXTRA_ARGS=--external-launcher&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_TOPOLIB=hwloc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_JOB_RESPECT_PROCESS_PLACEMENT=0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_BRANCH_COUNT=-1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_BOOTSTRAP=slurm&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_RETURN_WIN_MEM_NUMA=0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_PIN_DOMAIN=core&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_PIN_ORDER=scatter&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_INTERNAL_MEM_POLICY=default&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_DEBUG=10&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Each row of matrix is a mask for a Hardware Thread (hwt).&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;CORE ID&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= matrix digit + column group # in |...|&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;A set mask bit (proc-id) = core id + add 104 to each additional row.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;rank |&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;0&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;10&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;20&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;30&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;40&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;50&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;60&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;70&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;80&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;90&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;100 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;|&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0000 0-------------------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0001 --------8-----------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0002 ----------------6---------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0003 ------------------------4-------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 03 Jul 2024 15:09:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611893#M11782</guid>
      <dc:creator>ZQyou</dc:creator>
      <dc:date>2024-07-03T15:09:03Z</dc:date>
    </item>
    <item>
      <title>Re: Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611903#M11783</link>
      <description>&lt;P&gt;It seems you are using Slurm. If you are using Slurm, please use srun und manage pinning through Slurm.&lt;BR /&gt;&lt;BR /&gt;To use mpiexec/mpirun and ignore the Slurm settings please follow the settings here:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="https://www.intel.com/content/www/us/en/docs/mpi-library/developer-guide-linux/2021-13/job-schedulers-support.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/docs/mpi-library/developer-guide-linux/2021-13/job-schedulers-support.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 03 Jul 2024 15:56:20 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611903#M11783</guid>
      <dc:creator>TobiasK</dc:creator>
      <dc:date>2024-07-03T15:56:20Z</dc:date>
    </item>
    <item>
      <title>Re: Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611907#M11784</link>
      <description>&lt;P&gt;Yes, I am using Slurm, but I am sure that I have used the IntelMPI Hydra process manager. When I use Slurm, I have set the following:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;I_MPI_HYDRA_BOOTSTRAP=slurm&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;I_MPI_PMI_LIBRARY=/usr/lib64/libpmi2.so&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P class=""&gt;I had these settings to use the Hydra process manager when I obtained the previous output I sent:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;export&lt;/SPAN&gt;&lt;SPAN class=""&gt; -n I_MPI_HYDRA_BOOTSTRAP I_MPI_PMI_LIBRARY&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P&gt;I am confident because Slurm CPU binding control is not working.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I also tried using SSH as the Hydra bootstrap, but I got the same result.&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;$ export -n I_MPI_HYDRA_BOOTSTRAP I_MPI_PMI_LIBRARY &lt;BR /&gt;$ export I_MPI_HYDRA_BOOTSTRAP=ssh&lt;BR /&gt;$ mpiexec -n 4 bin/amask_mpi&lt;BR /&gt;&lt;BR /&gt;[0] MPI startup(): Intel(R) MPI Library, Version 2021.10&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;Build 20230619 (id: c2e19c2f3e)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Copyright (C) 2003-2023 Intel Corporation.&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;All rights reserved.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): library kind: release&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): shm segment size (342 MB per rank) * (4 local ranks) = 1368 MB total&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): libfabric loaded: libfabric.so.1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): libfabric version: 1.18.0-impi&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): max number of MPI_Request per vci: 67108864 (pools: 1)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): libfabric provider: mlx&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): File "/apps/spack/0.21/cardinal/linux-rhel9-sapphirerapids/intel-oneapi-mpi/intel/2021.10.0/2021.10.0-a2ei2t4/mpi/2021.10.0/etc/tuning_spr_shm-ofi_mlx_100.dat" not found&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Load tuning file: "/apps/spack/0.21/cardinal/linux-rhel9-sapphirerapids/intel-oneapi-mpi/intel/2021.10.0/2021.10.0-a2ei2t4/mpi/2021.10.0/etc/tuning_spr_shm-ofi.dat"&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: mode: direct&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: vcis: 1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: app_threads: -1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: runtime: generic&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: progress_threads: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: async_progress: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): threading: lock_level: global&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): tag bits available: 20 (TAG_UB value: 1048575)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): source bits available: 21 (Maximal number of rank: 2097151)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): Rank&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Pid&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Node name&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Pin cpu&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 0 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;783094 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{0}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 1 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;783095 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{8}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 2 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;783096 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{16}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): 3 &lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;783097 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;c1002.ten.osc.edu&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;{24}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_CC=icc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_CXX=icpc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_FC=ifort&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_F90=ifort&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_F77=ifort&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_ROOT=/apps/spack/0.21/cardinal/linux-rhel9-sapphirerapids/intel-oneapi-mpi/intel/2021.10.0/2021.10.0-a2ei2t4/mpi/2021.10.0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_BIND_WIN_ALLOCATE=localalloc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_BOOTSTRAP_EXEC_EXTRA_ARGS=--external-launcher&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_TOPOLIB=hwloc&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_JOB_RESPECT_PROCESS_PLACEMENT=0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_BRANCH_COUNT=-1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_HYDRA_BOOTSTRAP=ssh&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_RETURN_WIN_MEM_NUMA=0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_PIN_DOMAIN=core&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_PIN_ORDER=scatter&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_INTERNAL_MEM_POLICY=default&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;[0] MPI startup(): I_MPI_DEBUG=10&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;Each row of matrix is a mask for a Hardware Thread (hwt).&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;CORE ID&lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;= matrix digit + column group # in |...|&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;A set mask bit (proc-id) = core id + add 104 to each additional row.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;rank |&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;0&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;10&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;20&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;30&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;40&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;50&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;60&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;70&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;80&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;90&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;| &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;100 &lt;SPAN class=""&gt;&amp;nbsp; &lt;/SPAN&gt;|&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0000 0-------------------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0001 --------8-----------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0002 ----------------6---------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class=""&gt;0003 ------------------------4-------------------------------------------------------------------------------&lt;/SPAN&gt;&amp;nbsp;&lt;/PRE&gt;</description>
      <pubDate>Wed, 03 Jul 2024 16:21:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1611907#M11784</guid>
      <dc:creator>ZQyou</dc:creator>
      <dc:date>2024-07-03T16:21:52Z</dc:date>
    </item>
    <item>
      <title>Re: Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1612965#M11791</link>
      <description>&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/365617"&gt;@ZQyouOSC&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;can you please try the pinning simulator:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="https://www.intel.com/content/www/us/en/developer/tools/oneapi/mpi-library-pinning-simulator.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/developer/tools/oneapi/mpi-library-pinning-simulator.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Also please set&lt;BR /&gt;I_MPI_PIN_RESPECT_HCA=0&lt;BR /&gt;I_MPI_PIN_RESPECT_CPUSET=0&lt;BR /&gt;&lt;BR /&gt;Best&lt;/P&gt;</description>
      <pubDate>Mon, 08 Jul 2024 10:28:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1612965#M11791</guid>
      <dc:creator>TobiasK</dc:creator>
      <dc:date>2024-07-08T10:28:50Z</dc:date>
    </item>
    <item>
      <title>Re: Scatter the processes across sockets</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1613909#M11798</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I have tried the simulator, and it suggests the following command line to achieve scatter pinning across sockets:&lt;/P&gt;&lt;PRE&gt;I_MPI_PIN_DOMAIN=core I_MPI_PIN_ORDER=scatter I_MPI_PIN_CELL=unit mpiexec -n 4&lt;/PRE&gt;&lt;P&gt;I used the same environment variables along with the other two you suggested previously. However, I still got the compact-order result as I reported.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 10 Jul 2024 18:03:10 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/Scatter-the-processes-across-sockets/m-p/1613909#M11798</guid>
      <dc:creator>ZQyouOSC</dc:creator>
      <dc:date>2024-07-10T18:03:10Z</dc:date>
    </item>
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