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    <title>topic Re: NUMA node specific in Intel® MPI Library</title>
    <link>https://community.intel.com/t5/Intel-MPI-Library/NUMA-node-specific/m-p/1641344#M11977</link>
    <description>&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/156244"&gt;@Inspur&lt;/a&gt;&amp;nbsp;please use the priority support channel for such requests. At the moment, the way you propose with numactl is the preferred way.&lt;/P&gt;</description>
    <pubDate>Tue, 05 Nov 2024 12:23:22 GMT</pubDate>
    <dc:creator>TobiasK</dc:creator>
    <dc:date>2024-11-05T12:23:22Z</dc:date>
    <item>
      <title>NUMA node specific</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/NUMA-node-specific/m-p/1639212#M11961</link>
      <description>&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;We have a cluster node equiped with two CXL memory cards (each contains 8 x DDR5 4800MHz memory). In the OS, the two CXL cards' memory are shown as two new NUMA nodes, where the OS has 6 NUMA nodes in total (4 DDR NUMA + 2 CXL NUMA).&lt;/P&gt;&lt;P&gt;For the memory-bandwidth limited MPI applications, we want to apply the memory interleaving within some MPI processes to achieve higher memory bandwidth. In our test, coupled `mpirun` + `numactl` is effective for the pure MPI applications. For example, the CFD application OpenFOAM could use following command to run with DDR numa node.&lt;/P&gt;&lt;LI-CODE lang="bash"&gt;mpirun -n 64 simpleFoam -parallel&lt;/LI-CODE&gt;&lt;P&gt;To utilize the CXL memory with DDR memory, we utilize the numactl command before and after the mpirun command as follows.&lt;/P&gt;&lt;LI-CODE lang="bash"&gt;numactl --weighted-interleave=0-5 mpirun -n 64 simpleFoam -parallel&lt;/LI-CODE&gt;&lt;P&gt;or&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="bash"&gt;mpirun -n 64 numactl --weighted-interleave=0-5 simpleFoam -parallel&lt;/LI-CODE&gt;&lt;P&gt;With the CXL + DDR numa node, the OpenFOAM could achieve higher performance with higher bandwidth then the DDR memory bandwidth.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However, we want to specific the CXL numa node within the MPI Memory Policy Control environment variables, such as I_MPI_BIND_NUMA and I_MPI_BIND_ORDER. It wired that the performance does not change when we utilize these environments as follows.&lt;/P&gt;&lt;LI-CODE lang="bash"&gt;export I_MPI_BIND_NUMA=0-5
export I_MPI_BIND_ORDER=scatter&lt;/LI-CODE&gt;&lt;P&gt;We want to know how to specific the numa node for each processor, and could we defined the interleave weight parameters for multiply numa node?&lt;/P&gt;&lt;P&gt;For example:&lt;/P&gt;&lt;LI-CODE lang="bash"&gt;Rank 0-15  : NUMA node 0, 4; Weight 4, 1
Rank 16-31 : NUMA node 1, 4; Weight 4, 1
Rank 32-47 : NUMA node 2, 5; Weight 4, 1
Rank 48-63 : NUMA node 3, 5; Weight 4, 1&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Oct 2024 08:24:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/NUMA-node-specific/m-p/1639212#M11961</guid>
      <dc:creator>Inspur</dc:creator>
      <dc:date>2024-10-25T08:24:46Z</dc:date>
    </item>
    <item>
      <title>Re: NUMA node specific</title>
      <link>https://community.intel.com/t5/Intel-MPI-Library/NUMA-node-specific/m-p/1641344#M11977</link>
      <description>&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/156244"&gt;@Inspur&lt;/a&gt;&amp;nbsp;please use the priority support channel for such requests. At the moment, the way you propose with numactl is the preferred way.&lt;/P&gt;</description>
      <pubDate>Tue, 05 Nov 2024 12:23:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-MPI-Library/NUMA-node-specific/m-p/1641344#M11977</guid>
      <dc:creator>TobiasK</dc:creator>
      <dc:date>2024-11-05T12:23:22Z</dc:date>
    </item>
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