topic L3 caches in Nehalem in Intel® MPI Library

L3 caches in Nehalem

Aastha_Mehta — Tue, 15 Jun 2010 20:40:47 GMT

Hello,

I would like to know if any presently available tool can be used to get the L3 cache misses numbers from the performance counters of Nehalem based architecture? Also, is it possible to identify the exact point in the execution of a program when this L3 cache miss occurs?

Thanks in advance,

Aastha.

L3 caches in Nehalem

gert_massa — Wed, 16 Jun 2010 13:32:01 GMT

Vtune (make sure you have the latest version)

Not sure but I think these event couters are what you need:
LONGEST_LAT_CACHE.MISS and LONGEST_LAT_CACHE.REFERENCE

Otherwise have a look in OFFCORE_RESPONSE_0 but the help is not realy helpfull to understand all the different counters you can use.

L3 caches in Nehalem

gert_massa — Wed, 16 Jun 2010 13:51:30 GMT

These should also do the job according to the Perfromance Analysis Guide

Mem_inst_retired.latency_above_threshold_32
Mem_inst_retired.latency_above_threshold_128

P.S. This in a bit offtopic in the part of the forum. You should go to the Intel VTune Performance Analyzer

L3 caches in Nehalem

Aastha_Mehta — Thu, 17 Jun 2010 10:01:06 GMT

Thanks for the reply. First of all, should I move this thread to VTune Performance Analyzer forum then?

The L3_LAT_CACHE.REFERENCE and L3_LAT_CACHE.MISS are indeed the performance counters I would need to look at. I understand that I can read the values of these counters using RDMSR. Is this correct? And is there any interrrupt or exception generated when these counters overflow?

L3 caches in Nehalem

gert_massa — Thu, 17 Jun 2010 13:06:33 GMT

Just use VTune. It is worth every cent ;)

L3 caches in Nehalem

Aastha_Mehta — Fri, 18 Jun 2010 09:40:05 GMT

ok :)
but, i do need to go into the architectural details, so i am pursuing this.

i need to know what type of interrupts are generated on overflow of the performance counters and what data is available to the exception handlers for these. i figured out something like, there is a INT bit (bit 22) in the IA32_PERFEVTSELx MSR that you are using for monitoring your event, which is set when the corresponding PMC overflows and a local APIC interrupt is generated.

and if a performance counter is configured for PEBS, overflow condition in the counter generates a performance monitoring interrupt signalling a PEBS event.

are these two same things?

and i think L3_LAT_CACHE.MISS and L3_LAT_CACHE.REFERENCE are the events which have to be attached to IA32_PERFEVTSELx MSR and its associated IA32_PMCx MSR. you do not have separate counters for these events, right?