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    <title>topic Intel® MKL 2018 Beta Update 1 is now available in Intel® oneAPI Math Kernel Library</title>
    <link>https://community.intel.com/t5/Intel-oneAPI-Math-Kernel-Library/Intel-MKL-2018-Beta-Update-1-is-now-available/m-p/1083117#M22879</link>
    <description>&lt;P style="box-sizing: border-box; word-wrap: break-word; margin-bottom: 20px; line-height: 1.4; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; color: rgb(83, 87, 94);"&gt;Intel® MKL 2018 Beta is now available as part of the Parallel Studio XE 2018 Beta.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0.0001pt; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;Check the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="box-sizing: border-box"&gt;&lt;B&gt;&lt;SPAN style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&lt;A href="https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/731283" style="box-sizing: border-box;outline: none"&gt;&lt;SPAN lang="EN-US" style="font-weight: normal;"&gt;Join the Intel® Parallel Studio XE 2018 Beta program&lt;/SPAN&gt;&lt;/A&gt;&lt;/SPAN&gt;&lt;/B&gt;&lt;/SPAN&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&amp;nbsp;post to learn how to join the Beta program, and the provide your feedback.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0.0001pt; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;B style="font-size: 16.26px;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;What's New in Intel® MKL 2018 Beta Update 1:&lt;/SPAN&gt;&lt;/B&gt;&lt;/P&gt;

&lt;P&gt;BLAS:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Addressed an early release buffer issue in threaded *GEMV&lt;/LI&gt;
	&lt;LI&gt;Improved TBB *GEMM performance for small m and n while k is large&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;DNN:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Improved performance on Intel® Xeon Phi™ processor x200 (formerly Knights Landing)&lt;/LI&gt;
	&lt;LI&gt;Improved convolution performance for Intel(R) Xeon Phi™ processors based on&amp;nbsp;Intel®&amp;nbsp; Advanced Vector Extensions 512 (Intel®&amp;nbsp; AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;FFT:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Improved performance of 3D FFT complex-to-real and real-to-complex scaled and non-scaled problems on Intel® Xeon Phi™ processor 72** (formerly Knights Landing)&amp;nbsp;&lt;/LI&gt;
	&lt;LI&gt;Improved performance of 2D FFT complex-to-complex problems with scale on Intel® Xeon Phi™ processor 72** (formerly Knights Landing) and on Intel® Xeon processors E3-xxxx V5 (formerly SkyLake)&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;LAPACK:&amp;nbsp;&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Completed alignment with Netlib* LAPACK 3.7.0 by integrating all new routines and bug fixes. Notable new features are:
		&lt;UL style="list-style-type:circle;"&gt;
			&lt;LI&gt;Optimized factorization, solve and inverse routines with rook pivoting: ?sytrf_rk/?hetrf_rk, ?sytrs_rk/?hetrs_rk and ?sytri_3/?hetri_3&lt;/LI&gt;
			&lt;LI&gt;Added LAPACKE interfaces for all new routines including Aasen factorization and solve routines&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
	&lt;LI&gt;Improved ?gesvd performance for tall-and-skinny matrices.&lt;/LI&gt;
	&lt;LI&gt;Improved ?gelq/?gemlq&amp;nbsp; performance for short-and-wide matrices.&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;Vector Mathematics:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Improved performance of vdPowx and vsPowx functions for certain exponent values (0,5,6,7,8,9 )&lt;/LI&gt;
&lt;/UL&gt;

&lt;P style="margin: 0in 0in 0.0001pt; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0.25in; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial; box-sizing: border-box; max-width: none; word-wrap: break-word;"&gt;&lt;SPAN style="box-sizing: border-box"&gt;&lt;B&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;What's New in Intel® MKL 2018 Beta:&lt;/SPAN&gt;&lt;/B&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;DNN:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Added initial convolution and inner product optimizations for Intel(R) Xeon Phi(TM) processors based on Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups.&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Average pooling has an option to include padding into mean values computation&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;BLAS Features:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced optimized integer matrix-matrix multiplication routines (GEMM_S16S16S16 and GEMM_S16S16S32) to work with quantized matrices for all architectures.&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced ?TRSM_BATCH to complement the batched BLAS for all architectures&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;BLAS Optimizations:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Optimized SGEMM, GEMM_S16S16S16 and GEMM_S16S16S32 for Intel(R) Xeon Phi(TM) processors based on Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Improved ?GEMM_BATCH performance for all architectures&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Improved single and multi-threaded {D,S}SYMV performance for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) and the&amp;nbsp;Intel® Xeon Phi™ processor x200&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Sparse BLAS:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Improved performance of CSRMV/BSRMV functionality for Intel® AVX-512 instruction set in Inspector-Executor mode&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;LAPACK:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced factorization and solve routines based on Aasen's algorithm: ?sytrf_aa/?hetrf_aa, ?sytrs_aa/?hetrs_aa&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Vector Mathematics:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Added 24 new functions: v?Fmod, v?Remainder, v?Powr, v?Exp2; v?Exp10; v?Log2; v?Logb; v?Cospi; v?Sinpi; v?Tanpi; v?Acospi; v?Asinpi; v?Atanpi; v?Atan2pi; v?Cosd; v?Sind; v?Tand; v?CopySign; v?NextAfter; v?Fdim; v?Fmax; v?Fmin; v?MaxMag; v?MinMag&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Library Engineering:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced support for Intel(R) Xeon Phi(TM) processors based on Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups.&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;P style="box-sizing: border-box; word-wrap: break-word; margin-bottom: 20px; line-height: 1.4; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;Optimizations are not dispatched unless explicitly enabled with mkl_enable_instructions function call or MKL_ENABLE_INSTRUCTIONS environment variable.&lt;/P&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Documentation:&amp;nbsp;
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Starting with this version of Intel MKL, most of the documentation for Parallel Studio XE is only available online at &lt;A href="https://software.intel.com/en-us/articles/intel-math-kernel-library-documentation" target="_blank"&gt;https://software.intel.com/en-us/articles/intel-math-kernel-library-documentation&lt;/A&gt;. You can also download it from the Intel Registration Center &amp;gt; Product List &amp;gt; Intel® Parallel Studio XE Documentation Beta.&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;&lt;STRONG style="box-sizing: border-box;"&gt;Hardware Support for Intel® Xeon Phi™ Coprocessors (code name Knights Corner) is removed.&amp;nbsp;&lt;/STRONG&gt;Customers are recommended to stay on MKL 2017 given they continue to use and develop for Intel® Xeon Phi™ &amp;nbsp;Coprocessors (aka Knight Corner)&lt;/LI&gt;
&lt;/UL&gt;</description>
    <pubDate>Wed, 14 Jun 2017 07:09:57 GMT</pubDate>
    <dc:creator>Gennady_F_Intel</dc:creator>
    <dc:date>2017-06-14T07:09:57Z</dc:date>
    <item>
      <title>Intel® MKL 2018 Beta Update 1 is now available</title>
      <link>https://community.intel.com/t5/Intel-oneAPI-Math-Kernel-Library/Intel-MKL-2018-Beta-Update-1-is-now-available/m-p/1083117#M22879</link>
      <description>&lt;P style="box-sizing: border-box; word-wrap: break-word; margin-bottom: 20px; line-height: 1.4; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;&lt;SPAN style="font-family: Arial, sans-serif; font-size: 10pt; color: rgb(83, 87, 94);"&gt;Intel® MKL 2018 Beta is now available as part of the Parallel Studio XE 2018 Beta.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0.0001pt; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;Check the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="box-sizing: border-box"&gt;&lt;B&gt;&lt;SPAN style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&lt;A href="https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/731283" style="box-sizing: border-box;outline: none"&gt;&lt;SPAN lang="EN-US" style="font-weight: normal;"&gt;Join the Intel® Parallel Studio XE 2018 Beta program&lt;/SPAN&gt;&lt;/A&gt;&lt;/SPAN&gt;&lt;/B&gt;&lt;/SPAN&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&amp;nbsp;post to learn how to join the Beta program, and the provide your feedback.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0.0001pt; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;B style="font-size: 16.26px;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;What's New in Intel® MKL 2018 Beta Update 1:&lt;/SPAN&gt;&lt;/B&gt;&lt;/P&gt;

&lt;P&gt;BLAS:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Addressed an early release buffer issue in threaded *GEMV&lt;/LI&gt;
	&lt;LI&gt;Improved TBB *GEMM performance for small m and n while k is large&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;DNN:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Improved performance on Intel® Xeon Phi™ processor x200 (formerly Knights Landing)&lt;/LI&gt;
	&lt;LI&gt;Improved convolution performance for Intel(R) Xeon Phi™ processors based on&amp;nbsp;Intel®&amp;nbsp; Advanced Vector Extensions 512 (Intel®&amp;nbsp; AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;FFT:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Improved performance of 3D FFT complex-to-real and real-to-complex scaled and non-scaled problems on Intel® Xeon Phi™ processor 72** (formerly Knights Landing)&amp;nbsp;&lt;/LI&gt;
	&lt;LI&gt;Improved performance of 2D FFT complex-to-complex problems with scale on Intel® Xeon Phi™ processor 72** (formerly Knights Landing) and on Intel® Xeon processors E3-xxxx V5 (formerly SkyLake)&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;LAPACK:&amp;nbsp;&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Completed alignment with Netlib* LAPACK 3.7.0 by integrating all new routines and bug fixes. Notable new features are:
		&lt;UL style="list-style-type:circle;"&gt;
			&lt;LI&gt;Optimized factorization, solve and inverse routines with rook pivoting: ?sytrf_rk/?hetrf_rk, ?sytrs_rk/?hetrs_rk and ?sytri_3/?hetri_3&lt;/LI&gt;
			&lt;LI&gt;Added LAPACKE interfaces for all new routines including Aasen factorization and solve routines&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
	&lt;LI&gt;Improved ?gesvd performance for tall-and-skinny matrices.&lt;/LI&gt;
	&lt;LI&gt;Improved ?gelq/?gemlq&amp;nbsp; performance for short-and-wide matrices.&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;Vector Mathematics:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;Improved performance of vdPowx and vsPowx functions for certain exponent values (0,5,6,7,8,9 )&lt;/LI&gt;
&lt;/UL&gt;

&lt;P style="margin: 0in 0in 0.0001pt; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0.25in; background-image: initial; background-position: initial; background-size: initial; background-repeat: initial; background-attachment: initial; background-origin: initial; background-clip: initial; box-sizing: border-box; max-width: none; word-wrap: break-word;"&gt;&lt;SPAN style="box-sizing: border-box"&gt;&lt;B&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: Arial, sans-serif;"&gt;What's New in Intel® MKL 2018 Beta:&lt;/SPAN&gt;&lt;/B&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;DNN:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Added initial convolution and inner product optimizations for Intel(R) Xeon Phi(TM) processors based on Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups.&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Average pooling has an option to include padding into mean values computation&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;BLAS Features:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced optimized integer matrix-matrix multiplication routines (GEMM_S16S16S16 and GEMM_S16S16S32) to work with quantized matrices for all architectures.&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced ?TRSM_BATCH to complement the batched BLAS for all architectures&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;BLAS Optimizations:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Optimized SGEMM, GEMM_S16S16S16 and GEMM_S16S16S32 for Intel(R) Xeon Phi(TM) processors based on Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Improved ?GEMM_BATCH performance for all architectures&lt;/LI&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Improved single and multi-threaded {D,S}SYMV performance for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) and the&amp;nbsp;Intel® Xeon Phi™ processor x200&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Sparse BLAS:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Improved performance of CSRMV/BSRMV functionality for Intel® AVX-512 instruction set in Inspector-Executor mode&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;LAPACK:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced factorization and solve routines based on Aasen's algorithm: ?sytrf_aa/?hetrf_aa, ?sytrs_aa/?hetrs_aa&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Vector Mathematics:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Added 24 new functions: v?Fmod, v?Remainder, v?Powr, v?Exp2; v?Exp10; v?Log2; v?Logb; v?Cospi; v?Sinpi; v?Tanpi; v?Acospi; v?Asinpi; v?Atanpi; v?Atan2pi; v?Cosd; v?Sind; v?Tand; v?CopySign; v?NextAfter; v?Fdim; v?Fmax; v?Fmin; v?MaxMag; v?MinMag&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Library Engineering:
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Introduced support for Intel(R) Xeon Phi(TM) processors based on Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)&amp;nbsp;with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups.&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
&lt;/UL&gt;

&lt;P style="box-sizing: border-box; word-wrap: break-word; margin-bottom: 20px; line-height: 1.4; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;Optimizations are not dispatched unless explicitly enabled with mkl_enable_instructions function call or MKL_ENABLE_INSTRUCTIONS environment variable.&lt;/P&gt;

&lt;UL style="box-sizing: border-box; margin-top: 1.6em; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden; color: rgb(102, 102, 102); font-family: Arial, Tahoma, Helvetica, sans-serif; font-size: 14px;"&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Documentation:&amp;nbsp;
		&lt;UL style="box-sizing: border-box; margin-bottom: 20px; margin-left: 0px; padding-left: 30px; list-style-position: outside; overflow: hidden;"&gt;
			&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;Starting with this version of Intel MKL, most of the documentation for Parallel Studio XE is only available online at &lt;A href="https://software.intel.com/en-us/articles/intel-math-kernel-library-documentation" target="_blank"&gt;https://software.intel.com/en-us/articles/intel-math-kernel-library-documentation&lt;/A&gt;. You can also download it from the Intel Registration Center &amp;gt; Product List &amp;gt; Intel® Parallel Studio XE Documentation Beta.&lt;/LI&gt;
		&lt;/UL&gt;
	&lt;/LI&gt;
	&lt;LI style="box-sizing: border-box; margin-bottom: 10px; padding-left: 10px;"&gt;&lt;STRONG style="box-sizing: border-box;"&gt;Hardware Support for Intel® Xeon Phi™ Coprocessors (code name Knights Corner) is removed.&amp;nbsp;&lt;/STRONG&gt;Customers are recommended to stay on MKL 2017 given they continue to use and develop for Intel® Xeon Phi™ &amp;nbsp;Coprocessors (aka Knight Corner)&lt;/LI&gt;
&lt;/UL&gt;</description>
      <pubDate>Wed, 14 Jun 2017 07:09:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-oneAPI-Math-Kernel-Library/Intel-MKL-2018-Beta-Update-1-is-now-available/m-p/1083117#M22879</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2017-06-14T07:09:57Z</dc:date>
    </item>
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