<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Intel GPU BARRIER(CLK_GLOBAL_MEM_FENCE) behaviour in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/Intel-GPU-BARRIER-CLK-GLOBAL-MEM-FENCE-behaviour/m-p/936736#M1658</link>
    <description>Can anyone please direct me to a documentation source on the intel Ivy Bridge GPU?

Namely, I'm trying to figure out if BARRIER(CLK_GLOBAL_MEM_FENCE) will behave similarly to ADM or Nvidia devices. If there is an over-subscription of hardware threads will it draw a device deadlock with threads spinning on threads that cannot spawn reaching the barrier.


TY for your help.</description>
    <pubDate>Fri, 19 Apr 2013 18:17:07 GMT</pubDate>
    <dc:creator>andradx</dc:creator>
    <dc:date>2013-04-19T18:17:07Z</dc:date>
    <item>
      <title>Intel GPU BARRIER(CLK_GLOBAL_MEM_FENCE) behaviour</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Intel-GPU-BARRIER-CLK-GLOBAL-MEM-FENCE-behaviour/m-p/936736#M1658</link>
      <description>Can anyone please direct me to a documentation source on the intel Ivy Bridge GPU?

Namely, I'm trying to figure out if BARRIER(CLK_GLOBAL_MEM_FENCE) will behave similarly to ADM or Nvidia devices. If there is an over-subscription of hardware threads will it draw a device deadlock with threads spinning on threads that cannot spawn reaching the barrier.


TY for your help.</description>
      <pubDate>Fri, 19 Apr 2013 18:17:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Intel-GPU-BARRIER-CLK-GLOBAL-MEM-FENCE-behaviour/m-p/936736#M1658</guid>
      <dc:creator>andradx</dc:creator>
      <dc:date>2013-04-19T18:17:07Z</dc:date>
    </item>
    <item>
      <title>If workitems within a</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Intel-GPU-BARRIER-CLK-GLOBAL-MEM-FENCE-behaviour/m-p/936737#M1659</link>
      <description>&lt;P&gt;If workitems within a workgroup follow the same path ( e.g. when your barrier is under &lt;EM&gt;if&lt;/EM&gt;- clause), then no deadlock should occur by the best of my knowledge. All vendors follow the same OpenCL* pec so I suggest you rely on the specific description and recomendations from the OpenCL* standard as well.&lt;/P&gt;</description>
      <pubDate>Mon, 22 Apr 2013 07:18:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Intel-GPU-BARRIER-CLK-GLOBAL-MEM-FENCE-behaviour/m-p/936737#M1659</guid>
      <dc:creator>Maxim_S_Intel</dc:creator>
      <dc:date>2013-04-22T07:18:00Z</dc:date>
    </item>
  </channel>
</rss>

