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    <title>topic Thanks Michael for your in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/parallelism-degree/m-p/968627#M2350</link>
    <description>&lt;P&gt;Thanks Michael for your question.&lt;/P&gt;

&lt;P&gt;You are definately right. Each workgroup is implemented as a loop over the work-items. Then the loop is unrolled to the "float" SIMD width of the CPU. So double precision operations would need 2 SIMD egisters for each argument. This gives paralelism of 8 on today's CPUs (4 for doubles).&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;In addition, each CPU core can issue multiple different instructions rep cycle. The level of instuction level parallelism is dependent on the CPU model (generation) on the combination of instruction ready to execution at any given cycle and on the availeble CPU resources at that clock cycle. Hoever, the OpenCL compiler wouldn't expose such parallelism by additional loop untoling.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Arik&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 30 Jan 2014 14:56:44 GMT</pubDate>
    <dc:creator>Arik_N_Intel</dc:creator>
    <dc:date>2014-01-30T14:56:44Z</dc:date>
    <item>
      <title>parallelism degree?</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/parallelism-degree/m-p/968626#M2349</link>
      <description>&lt;P&gt;Dear all,&lt;/P&gt;

&lt;P&gt;&amp;nbsp;I try to know the number of parallel instruction involved in a OpenCL kernel regarding the kernel parameters... For instance, with 4-core Xeon, I launch 8 workgroup of 32 threads. (1 workgroup per HW thread).&amp;nbsp; We have so a parallelism degree of = 8 x parallelism degree of workgroup..&lt;/P&gt;

&lt;P&gt;What is the parallelism degree of a workgroup? I know that the code is scalarized and vectorized to fit with the xmm registers width.. And we must consider pipeline mechanism..&lt;/P&gt;

&lt;P&gt;Any idea?&lt;/P&gt;

&lt;P&gt;Regards, Michael&lt;/P&gt;</description>
      <pubDate>Mon, 27 Jan 2014 17:09:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/parallelism-degree/m-p/968626#M2349</guid>
      <dc:creator>Michael_B_</dc:creator>
      <dc:date>2014-01-27T17:09:41Z</dc:date>
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    <item>
      <title>Thanks Michael for your</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/parallelism-degree/m-p/968627#M2350</link>
      <description>&lt;P&gt;Thanks Michael for your question.&lt;/P&gt;

&lt;P&gt;You are definately right. Each workgroup is implemented as a loop over the work-items. Then the loop is unrolled to the "float" SIMD width of the CPU. So double precision operations would need 2 SIMD egisters for each argument. This gives paralelism of 8 on today's CPUs (4 for doubles).&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;In addition, each CPU core can issue multiple different instructions rep cycle. The level of instuction level parallelism is dependent on the CPU model (generation) on the combination of instruction ready to execution at any given cycle and on the availeble CPU resources at that clock cycle. Hoever, the OpenCL compiler wouldn't expose such parallelism by additional loop untoling.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Arik&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 30 Jan 2014 14:56:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/parallelism-degree/m-p/968627#M2350</guid>
      <dc:creator>Arik_N_Intel</dc:creator>
      <dc:date>2014-01-30T14:56:44Z</dc:date>
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