<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Hello, Robert Loffe. in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005214#M2934</link>
    <description>&lt;P&gt;Hello, Robert Loffe.&lt;/P&gt;

&lt;P&gt;Thanks for your reply, but I do not think there is a consistency between the CPU and GPU.&lt;/P&gt;

&lt;P&gt;Question 1:&lt;/P&gt;

&lt;P&gt;For example, I have a buffer int a[1024] and all elements are 0. Then I use the CPU kernel to increase each &amp;nbsp;odd elements such as a[1], a[3] and a[5]. I use the GPU kernel to decrease the even elements such as a[0], a[2] and a[4]. This process is in a for loop for 100 times. Because they are in the same cache line I cannot get correct results. But if they process different elements in different cache line, the result is right.&lt;/P&gt;

&lt;P&gt;I use the atomic_add and atomic_sub but it still get wrong. Does Intel does not implement Cache Coherency between CPU and GPU? Why? The only way I can handle this is to use clFinish() between the CPU kernel and GPU kernel. So it is serial.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Question 2:&lt;/P&gt;

&lt;P&gt;Does the GPU supports the double type? When I use double, clBuildProgram get wrong.&lt;/P&gt;

&lt;P&gt;I have add "#pragma OPENCL EXTENSION cl_khr_fp4 : enable" in the cl file.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thanks! Hope for your reply.&lt;/P&gt;</description>
    <pubDate>Tue, 09 Jun 2015 07:55:41 GMT</pubDate>
    <dc:creator>zhang_f_</dc:creator>
    <dc:date>2015-06-09T07:55:41Z</dc:date>
    <item>
      <title>How to perform Synchronization on Integrated GPU?</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005212#M2932</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I use OpenCL on&amp;nbsp;&lt;SPAN style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13.63636302948px; line-height: normal;"&gt;Intel® Core™ i7-4980HQ Processor.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13.63636302948px; line-height: normal;"&gt;The problem is:&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13.63636302948px; line-height: normal;"&gt;When the CPU and GPU write to the same cacheline, results sometimes get wrong.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13.63636302948px; line-height: normal;"&gt;The CPU and GPU both use OpenCL kernels.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;FONT color="#222222" face="arial, sans-serif"&gt;&lt;SPAN style="font-size: 13.63636302948px; line-height: normal;"&gt;Is there any mechanism to solve it? Atomic operation or something?&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;

&lt;P&gt;&lt;FONT color="#222222" face="arial, sans-serif"&gt;&lt;SPAN style="font-size: 13.63636302948px; line-height: normal;"&gt;Hope for your reply,&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;

&lt;P&gt;Thanks!&lt;/P&gt;</description>
      <pubDate>Sun, 17 May 2015 01:51:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005212#M2932</guid>
      <dc:creator>zhang_f_</dc:creator>
      <dc:date>2015-05-17T01:51:07Z</dc:date>
    </item>
    <item>
      <title>Hi Zhang,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005213#M2933</link>
      <description>&lt;P&gt;Hi Zhang,&lt;/P&gt;

&lt;P&gt;Sure, there are atomics. Check this link out: &lt;A href="https://www.khronos.org/registry/cl/sdk/1.2/docs/man/xhtml/atomicFunctions.html"&gt;https://www.khronos.org/registry/cl/sdk/1.2/docs/man/xhtml/atomicFunctions.html&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 18 May 2015 17:53:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005213#M2933</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-05-18T17:53:36Z</dc:date>
    </item>
    <item>
      <title>Hello, Robert Loffe.</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005214#M2934</link>
      <description>&lt;P&gt;Hello, Robert Loffe.&lt;/P&gt;

&lt;P&gt;Thanks for your reply, but I do not think there is a consistency between the CPU and GPU.&lt;/P&gt;

&lt;P&gt;Question 1:&lt;/P&gt;

&lt;P&gt;For example, I have a buffer int a[1024] and all elements are 0. Then I use the CPU kernel to increase each &amp;nbsp;odd elements such as a[1], a[3] and a[5]. I use the GPU kernel to decrease the even elements such as a[0], a[2] and a[4]. This process is in a for loop for 100 times. Because they are in the same cache line I cannot get correct results. But if they process different elements in different cache line, the result is right.&lt;/P&gt;

&lt;P&gt;I use the atomic_add and atomic_sub but it still get wrong. Does Intel does not implement Cache Coherency between CPU and GPU? Why? The only way I can handle this is to use clFinish() between the CPU kernel and GPU kernel. So it is serial.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Question 2:&lt;/P&gt;

&lt;P&gt;Does the GPU supports the double type? When I use double, clBuildProgram get wrong.&lt;/P&gt;

&lt;P&gt;I have add "#pragma OPENCL EXTENSION cl_khr_fp4 : enable" in the cl file.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thanks! Hope for your reply.&lt;/P&gt;</description>
      <pubDate>Tue, 09 Jun 2015 07:55:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005214#M2934</guid>
      <dc:creator>zhang_f_</dc:creator>
      <dc:date>2015-06-09T07:55:41Z</dc:date>
    </item>
    <item>
      <title>Hi Zhang,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005215#M2935</link>
      <description>&lt;P&gt;Hi Zhang,&lt;/P&gt;

&lt;P&gt;1. Atomics in OpenCL 1.2 are for syncing reads/writes to global memory from different work-items within the kernel, not for syncing between host and device reads/writes. For that you will need 5th Generation Intel(R) Processors (Broadwells) and OpenCL 2.0.&lt;/P&gt;

&lt;P&gt;Cache coherency in OpenCL 1.2 is only at synchronization points, which typically means at the end of kernel execution.&lt;/P&gt;

&lt;P&gt;2. GPU currently does not support ch_khr_fp64 (there is hardware, but support is not enabled in software). This extension is supported only on the CPU device right now.&lt;/P&gt;</description>
      <pubDate>Tue, 09 Jun 2015 21:45:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/How-to-perform-Synchronization-on-Integrated-GPU/m-p/1005215#M2935</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-06-09T21:45:12Z</dc:date>
    </item>
  </channel>
</rss>

