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    <title>topic Hi Kaj, in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009478#M3024</link>
    <description>&lt;P&gt;Hi Kaj,&lt;/P&gt;

&lt;P&gt;We have an internal discussion on what could have possibly gone wrong in your case. Could you please answer a couple of questions regarding your workload?&lt;/P&gt;

&lt;P&gt;1. Which earlier Intel HD devices have you tried?&lt;/P&gt;

&lt;P&gt;2. How did you create images previously vs how are you creating them now?&lt;/P&gt;

&lt;P&gt;3. What is the format of your images?&lt;/P&gt;

&lt;P&gt;4. What are the read_image and write_image commands inside your kernels? If you do multiple of them, what is the access pattern?&lt;/P&gt;

&lt;P&gt;This information will help us create a synthetic benchmark, since we are not in complete agreement as to what is going on in your case.&lt;/P&gt;

&lt;P&gt;Thank you very much in advance for your help!&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 15 Oct 2015 20:43:13 GMT</pubDate>
    <dc:creator>Robert_I_Intel</dc:creator>
    <dc:date>2015-10-15T20:43:13Z</dc:date>
    <item>
      <title>Interpreting the timeline in Platform analyzer?</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009470#M3016</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I am running my OpenCL application on an Intel HD 530 graphics device and experience exessive time usage for some kernels. On all previous devices I have tried (including earlier Intel HD), the measured time of my kernel during repeating calls has been fairly constant. On the HD 530 graphics, the execution time jumps between 3ms (normal) to 40ms(!).&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I got two questions:&lt;/P&gt;

&lt;OL&gt;
	&lt;LI&gt;In the attached sceren shot, the Platform Analyzer shows me the execution times for my kernels, but I don't know how I should interpret this, as each kernel is displayed several times, on different lines, with different execution times. Is the top line of colored boxes, the "actual execution time" and the lower ones indicate when the command was issued from CPU?&lt;/LI&gt;
	&lt;LI&gt;Do you have any idea why my execution time would jump between 3ms, which is the normal, and 40ms? When I enable more computation in my kernel I can see the 3ms is increasing, but the 40ms is constant. As I mentioned above, this has never happened on other devices (NVIDIA, AMD, Intel), which makes me think there is something else going on on the GPU.&lt;/LI&gt;
&lt;/OL&gt;

&lt;P&gt;Thanks&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&lt;IMG alt="Screen shot from Platform analyzer" src="F:\Intel INDE\OpenCL profiler.png" /&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Oct 2015 11:32:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009470#M3016</guid>
      <dc:creator>Weslien__Kaj-Robin</dc:creator>
      <dc:date>2015-10-08T11:32:05Z</dc:date>
    </item>
    <item>
      <title>Hi,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009471#M3017</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;Platform Analyzer is a fairly limited tool: what you see on the timeline is the GPU OpenCL command queue: you don't see the actual kernel running on the GPU. To get a better idea of what is going on, you can download Intel(R) VTune(TM) Amplifier 2016 &lt;A href="https://software.intel.com/en-us/intel-vtune-amplifier-xe/"&gt;https://software.intel.com/en-us/intel-vtune-amplifier-xe/&lt;/A&gt; - you can get a free 30-day evaluation version first to decided whether it is useful for your purposes.&lt;/P&gt;

&lt;P&gt;Then, take a look at this article : &lt;A href="https://software.intel.com/en-us/articles/intel-vtune-amplifier-xe-getting-started-with-opencl-performance-analysis-on-intel-hd-graphics"&gt;https://software.intel.com/en-us/articles/intel-vtune-amplifier-xe-getting-started-with-opencl-performance-analysis-on-intel-hd-graphics&lt;/A&gt; for a quick intro to using Vtune for OpenCL analysis.&lt;/P&gt;

&lt;P&gt;Please send me a screenshot of the Vtune analysis for a more complete picture.&lt;/P&gt;

&lt;P&gt;If you can provide me a sample reproducer (you can send it to me by private message) that would be even better.&lt;/P&gt;

&lt;P&gt;Also, please let me know the details of your system: the version of the graphics driver, the OS you are running on, whether your system is a laptop or a desktop, and whether you are measuring performance of your kernels while plugged in into a power source or not.&lt;/P&gt;</description>
      <pubDate>Thu, 08 Oct 2015 14:47:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009471#M3017</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-10-08T14:47:16Z</dc:date>
    </item>
    <item>
      <title>Hei,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009472#M3018</link>
      <description>&lt;P&gt;Hei,&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Thanks for answering fast. I am currently evaluating some new computers with these Intel chips, so I would need to sort this out before concluding if they are good enough.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Attached you'll find a screen shot from VTune showing the OpenCL compute queue. It is the "green kernel" in the graph that confuses me. Most often it spends 25ms doing apparently nothing (EU array stalled), but sometimes it executes in 1.6ms which is good.&lt;/P&gt;

&lt;P&gt;The fast execution (1.6ms is visible to the left in the graph and also marked in the list above, while a slow execution is visibble to the right and also in the list.&lt;/P&gt;

&lt;P&gt;I cannot ship any sample code at the moment.&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Here are some details on my system.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;I have tried on two separate desktop computers, both plugged in with power during profiling.&lt;/SPAN&gt;&lt;/P&gt;

&lt;OL&gt;
	&lt;LI&gt;Intel i7-6700T with HD530 graphics, Windows 7. Graphics driver version 10.18.15.4259&lt;BR /&gt;
		This is the one with the VTune screenshot attached.&lt;/LI&gt;
	&lt;LI&gt;Intel i5-6600T with HD530 graphica, Windows 10. Graphics driver "latest downloaded yesterday"&lt;/LI&gt;
&lt;/OL&gt;

&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Fri, 09 Oct 2015 09:14:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009472#M3018</guid>
      <dc:creator>Kaj_W_</dc:creator>
      <dc:date>2015-10-09T09:14:39Z</dc:date>
    </item>
    <item>
      <title>Hi Kaj,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009473#M3019</link>
      <description>&lt;P&gt;Hi Kaj,&lt;/P&gt;

&lt;P&gt;Well, looks like you are on the bleeding edge :) - first sighting of Skylake chips in the wild :)&lt;/P&gt;

&lt;P&gt;First, could you try the latest driver from here: &lt;A href="https://downloadcenter.intel.com/product/88345/Intel-HD-Graphics-530-for-6th-Generation-Intel-Core-Processors"&gt;https://downloadcenter.intel.com/product/88345/Intel-HD-Graphics-530-for-6th-Generation-Intel-Core-Processors&lt;/A&gt; - the driver version should be 15.40.7.4279? If you are still experiencing similar issues, we would need to figure out how to replicate the issue on our side: this could be still a driver issue, which may be fixed on the internal driver mainline (there is a lag of ~2 months between the released version of the driver and what's on the mainline) or it could be a hardware issue.&lt;/P&gt;

&lt;P&gt;We could get a non-disclosure agreement in place so that you can safely share your code with us or, if you can replicate the behavior on a simpler kernel that does not contain your IP, that would be great.&lt;/P&gt;</description>
      <pubDate>Fri, 09 Oct 2015 13:54:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009473#M3019</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-10-09T13:54:13Z</dc:date>
    </item>
    <item>
      <title>Hi,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009474#M3020</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;On the Windows 10 computer I was running the latest driver (&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;15.40.7.4279), but on the Win7 it would install properly. However there was no difference in behaviour.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;Anyway, I think I found the reason for the lagging behaviour. In my kernel I am working with images (image2d_t). I have multiple images that I read and one destination image that is written to. The source images are allocated with a 128 bytes/pixel alignment but my destination image could be of arbitary size. All images are in the order of ~1000-3000 pixels wide.&lt;BR /&gt;
	It turned out that at specific destination images sizes my kernel performed as expected. This suggests I should probably allocate all images using a width that is a multiple of N, where N is still unknown for me.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 12px; line-height: 18px;"&gt;I will do some reading to see if this multiple can be queried from the device. If you have any hints, feel free to post them :)&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;BR /&gt;
	&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 12 Oct 2015 13:16:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009474#M3020</guid>
      <dc:creator>Kaj_W_</dc:creator>
      <dc:date>2015-10-12T13:16:44Z</dc:date>
    </item>
    <item>
      <title>Kaj,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009475#M3021</link>
      <description>&lt;P&gt;Kaj,&lt;/P&gt;

&lt;P&gt;I think it is a good idea for N to be a multiple of 64 (or more precisely, that your width in bytes should be a multiple of 64 bytes, so depending on the size of your pixel, multiples of 16, 32, or 64 should be good). I am curious to know what image sizes give you trouble.&lt;/P&gt;</description>
      <pubDate>Mon, 12 Oct 2015 18:22:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009475#M3021</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-10-12T18:22:06Z</dc:date>
    </item>
    <item>
      <title>Kaj,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009476#M3022</link>
      <description>&lt;P&gt;Kaj,&lt;/P&gt;

&lt;P&gt;Here is an interesting explanation of your performance degradation from our performance engineer:&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;&lt;FONT face="Calibri" size="3"&gt;This VTUNE data points to BW limited. The low dispatch rate (GPU Computing Thread row) combined with the near 100% EU stalls (red line from GPU Execution Units row) implies this.&amp;nbsp; The kernel heavily uses images based on the elevated Texture Sample rate.&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;&lt;FONT face="Calibri" size="3"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;&lt;FONT face="Calibri" size="3"&gt;I’d guess that the long kernel execution time is due to a large number of cache misses.&amp;nbsp; If the data set used for this enqueue is not spatially localized then you will miss the Sampler cache, L3 cache, and maybe even LLC.&amp;nbsp; All access could potentially be fetched from DRAM.&amp;nbsp; SKL Sampler bandwidth is much higher that DRAM bandwidth.&amp;nbsp; This could explain why the same kernel is fast sometimes and slow other times.&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;&lt;FONT face="Calibri" size="3"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;FONT face="Calibri"&gt;&lt;FONT size="3"&gt;&lt;B&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;Experiment to test theory&lt;/SPAN&gt;&lt;/B&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;: Modify kernel to only sample from the same image coordinate (e.g. 0, 0).&amp;nbsp; If this makes all kernel enqueues fast then this supports the theory.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;&lt;FONT face="Calibri" size="3"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/P&gt;

&lt;P style="margin: 0in 0in 0pt;"&gt;&lt;FONT face="Calibri"&gt;&lt;FONT size="3"&gt;&lt;B&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;Why might this issue only be seen on SKL?&lt;/SPAN&gt;&lt;/B&gt;&lt;SPAN style="color: rgb(31, 73, 125);"&gt;&amp;nbsp; If the customer is comparing against only discrete cards then this issue may not be as observable.&amp;nbsp; Discrete cards have dedicated, fast access DRAM.&amp;nbsp; It’s expected that discrete cards will have an advantage on DRAM-BW-limited workloads over integrated graphics.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 14 Oct 2015 23:13:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009476#M3022</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-10-14T23:13:37Z</dc:date>
    </item>
    <item>
      <title>Thanks Robert, both for the</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009477#M3023</link>
      <description>&lt;P&gt;Thanks Robert, both for the hints about memory alignment (image width) and the explanation of my VTune screen shot.&lt;/P&gt;

&lt;P&gt;When using a multiple of 64 bytes my kernel does indeed run fast all the time. I get the impression the kernel struggles on all image widths except for the ones with correct alignment.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 15 Oct 2015 07:50:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009477#M3023</guid>
      <dc:creator>Kaj_W_</dc:creator>
      <dc:date>2015-10-15T07:50:24Z</dc:date>
    </item>
    <item>
      <title>Hi Kaj,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009478#M3024</link>
      <description>&lt;P&gt;Hi Kaj,&lt;/P&gt;

&lt;P&gt;We have an internal discussion on what could have possibly gone wrong in your case. Could you please answer a couple of questions regarding your workload?&lt;/P&gt;

&lt;P&gt;1. Which earlier Intel HD devices have you tried?&lt;/P&gt;

&lt;P&gt;2. How did you create images previously vs how are you creating them now?&lt;/P&gt;

&lt;P&gt;3. What is the format of your images?&lt;/P&gt;

&lt;P&gt;4. What are the read_image and write_image commands inside your kernels? If you do multiple of them, what is the access pattern?&lt;/P&gt;

&lt;P&gt;This information will help us create a synthetic benchmark, since we are not in complete agreement as to what is going on in your case.&lt;/P&gt;

&lt;P&gt;Thank you very much in advance for your help!&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 15 Oct 2015 20:43:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009478#M3024</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2015-10-15T20:43:13Z</dc:date>
    </item>
    <item>
      <title>Robert,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009479#M3025</link>
      <description>&lt;P&gt;Robert,&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I'll do my best to answer your questions.&lt;/P&gt;

&lt;OL&gt;
	&lt;LI&gt;I have previously tested the ones listed below. When running my tests on these I didn't observe the effect where kernel time jumped between high and low, as it did with the HD &amp;nbsp;530.&amp;nbsp;&lt;BR /&gt;
		HD 2500&lt;BR /&gt;
		HD 4000&lt;BR /&gt;
		HD 4600&lt;BR /&gt;
		HD 5000&lt;/LI&gt;
	&lt;LI&gt;More or less the same code has been used on all tests. At least when it comes to image creation and read/write operations.&amp;nbsp;&lt;/LI&gt;
	&lt;LI&gt;Here is how I create the images, and you can see the image format used:&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp; &amp;nbsp;cl_image_format imgFormat;&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp; &amp;nbsp;imgFormat.image_channel_data_type = CL_UNSIGNED_INT8;&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp; &amp;nbsp;imgFormat.image_channel_order = CL_R;&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp; &amp;nbsp;cl_int err;&lt;BR /&gt;
		&amp;nbsp;&amp;nbsp; &amp;nbsp;dIm = clCreateImage2D(context, CL_MEM_READ_WRITE, &amp;amp;imgFormat, width, height, 0, nullptr, &amp;amp;err);&lt;/LI&gt;
	&lt;LI&gt;I tried to simplify my kernel, and it boils down to something like this. pIm1-4 are all aligned to 128 bytes, but pDstIm has been of arbitary size when testing and always smaller than pIm1-4.&lt;BR /&gt;
		&amp;nbsp;
		&lt;P&gt;__kernel void myKernel(&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;__read_only &amp;nbsp;image2d_t pIm1,&amp;nbsp;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;__read_only &amp;nbsp;image2d_t pIm2,&amp;nbsp;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;__read_only &amp;nbsp;image2d_t pIm3,&amp;nbsp;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;__read_only &amp;nbsp;image2d_t pIm4,&amp;nbsp;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;__write_only image2d_t pDstIm,&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;const __global float* buf1,&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;const __global float* buf2,&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;const __global float* buf3,&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;int width,&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;int height&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;)&lt;BR /&gt;
			{&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;const sampler_t smp = CLK_NORMALIZED_COORDS_FALSE | CLK_ADDRESS_CLAMP_TO_EDGE | CLK_FILTER_LINEAR&amp;nbsp;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;const sampler_t smpNearest = CLK_NORMALIZED_COORDS_FALSE | CLK_ADDRESS_CLAMP_TO_EDGE | CLK_FILTER_NEAREST;&amp;nbsp;&lt;/P&gt;

		&lt;P&gt;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;int2 ptDst = (int2)(get_global_id(0), get_global_id(1));&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;int x = get_global_id(0);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;int y = get_global_id(1);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;if(x &amp;lt; width &amp;amp;&amp;amp; y &amp;lt; height)&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;{&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;float2 ptSrc = f(x, y);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;b1 = buf1[bIdx];&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;b2 = buf2[bIdx];&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;b3 = buf3[bIdx];&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;val1 = read_imageui(pIm1, smpNearest, ptSrc);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;val2 = read_imageui(pIm2, smp, ptSrc);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;val3 = read_imageui(pIm3, smp, ptSrc);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;val4 = read_imageui(pIm4, smp, ptSrc);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;val.x = g(val1, val2, val3, val4)&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;write_imageui(pDstIm, ptDst, val);&lt;BR /&gt;
			&amp;nbsp;&amp;nbsp; &amp;nbsp;}&lt;BR /&gt;
			}&lt;/P&gt;
		&lt;BR /&gt;
	&lt;/LI&gt;
&lt;/OL&gt;</description>
      <pubDate>Fri, 16 Oct 2015 06:02:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Interpreting-the-timeline-in-Platform-analyzer/m-p/1009479#M3025</guid>
      <dc:creator>Kaj_W_</dc:creator>
      <dc:date>2015-10-16T06:02:17Z</dc:date>
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