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    <title>topic Hi Zvi, in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/Serializing-2-kernels/m-p/1090134#M4873</link>
    <description>&lt;P&gt;Hi Zvi,&lt;/P&gt;

&lt;P&gt;Depends on your hardware. If you have 5th or 6th generation Intel processors (Broadwell or Skylake), which support OpenCL 2.0, you can enqueue the second kernel from the first one (see &lt;A href="https://software.intel.com/en-us/articles/gpu-quicksort-in-opencl-20-using-nested-parallelism-and-work-group-scan-functions"&gt;https://software.intel.com/en-us/articles/gpu-quicksort-in-opencl-20-using-nested-parallelism-and-work-group-scan-functions&lt;/A&gt; for example on how to do that or &lt;A href="https://software.intel.com/en-us/articles/sierpinski-carpet-in-opencl-20"&gt;https://software.intel.com/en-us/articles/sierpinski-carpet-in-opencl-20&lt;/A&gt; for a toy example).&lt;/P&gt;</description>
    <pubDate>Wed, 20 Jan 2016 00:19:38 GMT</pubDate>
    <dc:creator>Robert_I_Intel</dc:creator>
    <dc:date>2016-01-20T00:19:38Z</dc:date>
    <item>
      <title>Serializing 2 kernels</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Serializing-2-kernels/m-p/1090133#M4872</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;
	&lt;BR /&gt;
	My input data is N rows X M columns matrix. Each cell is a &lt;B&gt;float &lt;/B&gt;number.&lt;BR /&gt;
	&lt;BR /&gt;
	The first stage:&lt;BR /&gt;
	Subtract each row from its previous one.&lt;BR /&gt;
	The output data is (N-1) rows X M columns.&lt;BR /&gt;
	For the subtraction, I think (not sure) I have to keep the input matrix and put the output in a new matrix.&lt;BR /&gt;
	&lt;BR /&gt;
	Second stage:&lt;BR /&gt;
	FFT on each row. The output is (N-1) rows X M columns.&lt;BR /&gt;
	For the FFT process, the work item is a butterfly. for M items in a row I have M/4 butterflies.&lt;BR /&gt;
	&lt;BR /&gt;
	Is it possible to do the 2 operations without coming back to the host after the first stage ?&lt;BR /&gt;
	&lt;BR /&gt;
	Best regards,&lt;BR /&gt;
	Z.V&lt;/P&gt;</description>
      <pubDate>Sun, 17 Jan 2016 03:42:02 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Serializing-2-kernels/m-p/1090133#M4872</guid>
      <dc:creator>ZVere</dc:creator>
      <dc:date>2016-01-17T03:42:02Z</dc:date>
    </item>
    <item>
      <title>Hi Zvi,</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Serializing-2-kernels/m-p/1090134#M4873</link>
      <description>&lt;P&gt;Hi Zvi,&lt;/P&gt;

&lt;P&gt;Depends on your hardware. If you have 5th or 6th generation Intel processors (Broadwell or Skylake), which support OpenCL 2.0, you can enqueue the second kernel from the first one (see &lt;A href="https://software.intel.com/en-us/articles/gpu-quicksort-in-opencl-20-using-nested-parallelism-and-work-group-scan-functions"&gt;https://software.intel.com/en-us/articles/gpu-quicksort-in-opencl-20-using-nested-parallelism-and-work-group-scan-functions&lt;/A&gt; for example on how to do that or &lt;A href="https://software.intel.com/en-us/articles/sierpinski-carpet-in-opencl-20"&gt;https://software.intel.com/en-us/articles/sierpinski-carpet-in-opencl-20&lt;/A&gt; for a toy example).&lt;/P&gt;</description>
      <pubDate>Wed, 20 Jan 2016 00:19:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Serializing-2-kernels/m-p/1090134#M4873</guid>
      <dc:creator>Robert_I_Intel</dc:creator>
      <dc:date>2016-01-20T00:19:38Z</dc:date>
    </item>
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