<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic __private memory, spills and loop unrolling on HD Graphics in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116378#M5406</link>
    <description>&lt;P&gt;I have a few questions:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;If IOC reports that private memory is being used then does that always imply that it's being spilled or can it reside in the remaining registers?&lt;/LI&gt;
	&lt;LI&gt;How do I detect or analyze my kernel to see if spilling is occurring?&lt;/LI&gt;
	&lt;LI&gt;Should an auto struct multidimensional array of registers (some dimensions are 1) that is always indexed with constants be automatically fully unrolled (and not appear as private memory)?&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;I'm seeing a lot of mov and send operations in the .asm dump -- more than I would expect -- and would like to understand what's happening in the kernel and how to get the auto variable struct to be "stationary" in the register file since all the accesses are constant.&lt;/P&gt;

&lt;P&gt;This is on GEN9 / Win10/x64 and the latest driver.&lt;/P&gt;

&lt;P&gt;One high point: &amp;nbsp;half floats seem to work OK!&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Allan&lt;/P&gt;</description>
    <pubDate>Thu, 15 Dec 2016 22:31:56 GMT</pubDate>
    <dc:creator>allanmac1</dc:creator>
    <dc:date>2016-12-15T22:31:56Z</dc:date>
    <item>
      <title>__private memory, spills and loop unrolling on HD Graphics</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116378#M5406</link>
      <description>&lt;P&gt;I have a few questions:&lt;/P&gt;

&lt;UL&gt;
	&lt;LI&gt;If IOC reports that private memory is being used then does that always imply that it's being spilled or can it reside in the remaining registers?&lt;/LI&gt;
	&lt;LI&gt;How do I detect or analyze my kernel to see if spilling is occurring?&lt;/LI&gt;
	&lt;LI&gt;Should an auto struct multidimensional array of registers (some dimensions are 1) that is always indexed with constants be automatically fully unrolled (and not appear as private memory)?&lt;/LI&gt;
&lt;/UL&gt;

&lt;P&gt;I'm seeing a lot of mov and send operations in the .asm dump -- more than I would expect -- and would like to understand what's happening in the kernel and how to get the auto variable struct to be "stationary" in the register file since all the accesses are constant.&lt;/P&gt;

&lt;P&gt;This is on GEN9 / Win10/x64 and the latest driver.&lt;/P&gt;

&lt;P&gt;One high point: &amp;nbsp;half floats seem to work OK!&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Allan&lt;/P&gt;</description>
      <pubDate>Thu, 15 Dec 2016 22:31:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116378#M5406</guid>
      <dc:creator>allanmac1</dc:creator>
      <dc:date>2016-12-15T22:31:56Z</dc:date>
    </item>
    <item>
      <title>I was able to reduce private</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116379#M5407</link>
      <description>&lt;P&gt;I was able to reduce private memory to zero in my kernel by significantly simplifying the struct automatic variable and using&amp;nbsp;__attribute__((opencl_unroll_hint(n))).&lt;/P&gt;</description>
      <pubDate>Fri, 16 Dec 2016 22:14:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116379#M5407</guid>
      <dc:creator>allanmac1</dc:creator>
      <dc:date>2016-12-16T22:14:05Z</dc:date>
    </item>
    <item>
      <title>There is an Intel extension</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116380#M5408</link>
      <description>&lt;P&gt;There is an Intel extension that may help you identify answers for your first two questions.&lt;/P&gt;

&lt;P&gt;Extensions doc is here:&lt;/P&gt;

&lt;P&gt;&lt;A href="https://www.khronos.org/registry/cl/extensions/intel/cl_intel_driver_diagnostics.txt" target="_blank"&gt;https://www.khronos.org/registry/cl/extensions/intel/cl_intel_driver_diagnostics.txt&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Here is a sample code:&lt;/P&gt;

&lt;P&gt;&lt;A href="https://software.intel.com/en-us/articles/application-performance-using-intel-opencl-driver-diagnostics-sample-users-guide" target="_blank"&gt;https://software.intel.com/en-us/articles/application-performance-using-intel-opencl-driver-diagnostics-sample-users-guide&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;You are looking for "bad" diagnostic messages, they will be generated upon clCreateKernel if:&lt;/P&gt;

&lt;P&gt;- compiler during compilation of the kernel ran out of register space and additional surface for spill fills is required, if message is not present there are no spill fills.&lt;/P&gt;

&lt;P&gt;- the amount of private memory that kernel uses doesn't fit into registers and global memory allocation needs to be created, if you don't see this diagnostic message it means that private memory is in registers.&lt;/P&gt;</description>
      <pubDate>Mon, 02 Jan 2017 19:58:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116380#M5408</guid>
      <dc:creator>Michal_M_Intel</dc:creator>
      <dc:date>2017-01-02T19:58:49Z</dc:date>
    </item>
    <item>
      <title>That was nice and easy to</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116381#M5409</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 1em;"&gt;That was nice and easy to implement. &amp;nbsp;The Intel driver is full of neat features.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;I was already printing spill size info via CL_KERNEL_SPILL_MEM_SIZE_INTEL and know that my kernel is suffering from spills so I'm wondering how to interpret the "additional surface needs to be allocated" followed by 1012 KB (why 1012 KB?).&lt;/P&gt;

&lt;BLOCKQUOTE&gt;
	&lt;P&gt;Performance hint: Kernel xyz_kernel register pressure is too high, spill fills will be generated, additional surface needs to be allocated of size 1036288, consider simplifying your kernel.&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;

&lt;P&gt;&lt;SPAN style="font-size: 13.008px;"&gt;Thanks!&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 03 Jan 2017 16:55:53 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116381#M5409</guid>
      <dc:creator>allanmac1</dc:creator>
      <dc:date>2017-01-03T16:55:53Z</dc:date>
    </item>
    <item>
      <title>Thanks for feedback.</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116382#M5410</link>
      <description>&lt;P&gt;Thanks for feedback.&lt;/P&gt;

&lt;P style="font-size: 13.008px;"&gt;&lt;SPAN style="font-size: 12px;"&gt;CL_KERNEL_SPILL_MEM_SIZE_INTEL tells you how much each Hardware Thread is spilling.&lt;/SPAN&gt;&lt;/P&gt;

&lt;DIV&gt;Value reported by driver diagnostics is in fact&amp;nbsp;&lt;SPAN style="font-size: 12px;"&gt;CL_KERNEL_SPILL_MEM_SIZE_INTEL multiplied by the number of Hardware Threads your device has with some padding.&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 04 Jan 2017 14:39:02 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/private-memory-spills-and-loop-unrolling-on-HD-Graphics/m-p/1116382#M5410</guid>
      <dc:creator>Michal_M_Intel</dc:creator>
      <dc:date>2017-01-04T14:39:02Z</dc:date>
    </item>
  </channel>
</rss>

