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    <title>topic Sandy Bridge CPU &amp; Native vector width in OpenCL* for CPU</title>
    <link>https://community.intel.com/t5/OpenCL-for-CPU/Sandy-Bridge-CPU-Native-vector-width/m-p/813966#M942</link>
    <description>&lt;P class="sectionbody"&gt;Thanks for pointing that,&lt;/P&gt;&lt;P class="sectionbody"&gt;The behavior you see on Sandy Bridge CPU is as expected with
this Beta.&lt;/P&gt;&lt;P class="sectionbody"&gt;As the install based of Sandy Bridge will increase and mature
into to the domains where OpenCL based floating-point applications are in used,
we will extend our support.&lt;/P&gt;&lt;P class="sectionbody"&gt;So yes, the behaviour is
not yet implemented and will be added in future versions.&lt;/P&gt;

&lt;P class="sectionbody"&gt;Thanks,&lt;/P&gt;

&lt;P class="sectionbody"&gt;-
Arnon&lt;/P&gt;</description>
    <pubDate>Wed, 01 Jun 2011 14:53:05 GMT</pubDate>
    <dc:creator>ARNON_P_Intel</dc:creator>
    <dc:date>2011-06-01T14:53:05Z</dc:date>
    <item>
      <title>Sandy Bridge CPU &amp; Native vector width</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Sandy-Bridge-CPU-Native-vector-width/m-p/813965#M941</link>
      <description>Hello,&lt;BR /&gt;&lt;BR /&gt;I originally tried the SDK on Linux on a dual-socket Harpertown, where CL reports the preferred &amp;amp; native width for all datatypes as 16 bytes, i.e. from 16 chars to 2 doubles. That's what fit inside a XMM register, which is what I expected.&lt;BR /&gt;&lt;BR /&gt;But after checking the values on a Sandy Bridge CPU (i5-2400), I get the same preferred &amp;amp; native sizes. This seems strange to me, as my understanding of the architecture is that if the dataset is large enough and floating-point, one should go for AVX instead of SSE. There is very little support for integer stuff in YMM registers, so I understand that char/short/int/long are still 16/8/4/2, but shouldn't float/double be 8/4 rather than 4/2?&lt;BR /&gt;&lt;BR /&gt;Is it deliberate and if so why, or is it just a case of "we haven't had time to implement it yet"?&lt;BR /&gt;&lt;BR /&gt;Cordially,</description>
      <pubDate>Tue, 31 May 2011 10:19:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Sandy-Bridge-CPU-Native-vector-width/m-p/813965#M941</guid>
      <dc:creator>Romain_D_</dc:creator>
      <dc:date>2011-05-31T10:19:58Z</dc:date>
    </item>
    <item>
      <title>Sandy Bridge CPU &amp; Native vector width</title>
      <link>https://community.intel.com/t5/OpenCL-for-CPU/Sandy-Bridge-CPU-Native-vector-width/m-p/813966#M942</link>
      <description>&lt;P class="sectionbody"&gt;Thanks for pointing that,&lt;/P&gt;&lt;P class="sectionbody"&gt;The behavior you see on Sandy Bridge CPU is as expected with
this Beta.&lt;/P&gt;&lt;P class="sectionbody"&gt;As the install based of Sandy Bridge will increase and mature
into to the domains where OpenCL based floating-point applications are in used,
we will extend our support.&lt;/P&gt;&lt;P class="sectionbody"&gt;So yes, the behaviour is
not yet implemented and will be added in future versions.&lt;/P&gt;

&lt;P class="sectionbody"&gt;Thanks,&lt;/P&gt;

&lt;P class="sectionbody"&gt;-
Arnon&lt;/P&gt;</description>
      <pubDate>Wed, 01 Jun 2011 14:53:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/OpenCL-for-CPU/Sandy-Bridge-CPU-Native-vector-width/m-p/813966#M942</guid>
      <dc:creator>ARNON_P_Intel</dc:creator>
      <dc:date>2011-06-01T14:53:05Z</dc:date>
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