https://community.intel.com/t5/Mobile-and-Desktop-Processors/Opcode-semantics/m-p/190691#M163 <P>Hi,</P><P></P><P>Firstly, I apologize if this is the wrong forum; I could not find any other more relevant.</P><P></P><P>I'm looking for clarification in regards to a statement made that asserts there is a 1-cycle difference between the instructions:</P><P></P><P>0x3B (cmp reg, mem)</P><P>0x39 (cmp mem, reg)</P><P></P><P>As the two are functionally equivalent, I assume it would have to have something to do with the decoding circuit logic, but would like clarification if this statement reigns true in the first place.</P><P></P><P>Additionally, if this is true, where would I be able to find documentation of such details? All of the manuals I've read (even the IA32 optimization manual) does not mention these things.</P><P></P><P>Thanks,</P><P></P><P>Matt.</P> Thu, 13 Aug 2009 08:32:20 GMT idata 2009-08-13T08:32:20Z https://community.intel.com/t5/Mobile-and-Desktop-Processors/Opcode-semantics/m-p/190691#M163 <P>Hi,</P><P></P><P>Firstly, I apologize if this is the wrong forum; I could not find any other more relevant.</P><P></P><P>I'm looking for clarification in regards to a statement made that asserts there is a 1-cycle difference between the instructions:</P><P></P><P>0x3B (cmp reg, mem)</P><P>0x39 (cmp mem, reg)</P><P></P><P>As the two are functionally equivalent, I assume it would have to have something to do with the decoding circuit logic, but would like clarification if this statement reigns true in the first place.</P><P></P><P>Additionally, if this is true, where would I be able to find documentation of such details? All of the manuals I've read (even the IA32 optimization manual) does not mention these things.</P><P></P><P>Thanks,</P><P></P><P>Matt.</P> Thu, 13 Aug 2009 08:32:20 GMT https://community.intel.com/t5/Mobile-and-Desktop-Processors/Opcode-semantics/m-p/190691#M163 idata 2009-08-13T08:32:20Z