Interpreting Intel Memory Latency Checker Output.

vvaib — Wed, 05 Oct 2016 18:12:32 GMT

I am using a dual socket Xeon E5- 2650 machine with 32 GB of memory (Numa Node). I have been wanting to determine

the memory latency for a CPU located in node 0 and memory allocated in node 1 and vice versa. Below is the output of MLC.

./mlc –c0 –i9

Intel(R) Memory Latency Checker - v3.1a

Measuring idle latencies (in ns)...

Numa node

Numa node 0 1

0 69.4 118.4

1 120.9 69.8

Measuring Peak Memory Bandwidths for the system

Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)

Using all the threads from each core if Hyper-threading is enabled

Using traffic with the following read-write ratios

ALL Reads : 84419.1

3:1 Reads-Writes : 78571.6

2:1 Reads-Writes : 77405.7

1:1 Reads-Writes : 76944.3

Stream-triad like: 71137.4

Measuring Memory Bandwidths between nodes within system

Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)

Using all the threads from each core if Hyper-threading is enabled

Using Read-only traffic type

Numa node

Numa node 0 1

0 42956.4 20636.6

1 20434.2 42859.2

Measuring Loaded Latencies for the system

Using all the threads from each core if Hyper-threading is enabled

Using Read-only traffic type

Inject Latency Bandwidth

Delay (ns) MB/sec

==========================

00000 162.49 84301.1

00002 161.99 84227.3

00008 159.84 83922.1

00015 156.98 83520.4

00050 111.13 68611.6

00100 99.14 50781.7

00200 92.75 33050.8

00300 89.26 24573.0

00400 87.29 19625.5

00500 85.81 16389.1

00700 82.69 12398.8

01000 82.53 9169.0

01300 81.64 7352.0

01700 80.25 5888.5

02500 79.06 4325.2

03500 78.10 3357.7

05000 77.66 2613.2

09000 76.99 1832.3

20000 76.52 1289.1

Measuring cache-to-cache transfer latency (in ns)...

Local Socket L2->L2 HIT latency 31.4

Local Socket L2->L2 HITM latency 35.8

Remote Socket LLC->LLC HITM latency (data address homed in writer socket)

Reader Numa Node

Writer Numa Node 0 1

0 - 130.7

1 129.4 -

Remote Socket LLC->LLC HITM latency (data address homed in reader socket)

Reader Numa Node

Writer Numa Node 0 1

0 - 80.5

1 79.7 -

From this, how can I get the desired latencies?

Thanks.

Re: Interpreting Intel Memory Latency Checker Output.

idata — Thu, 06 Oct 2016 19:16:18 GMT

In order to address any inquiry in regard to the Intel® Memory Latency Checker, you need to contact our Software developer team.

https://software.intel.com/en-us/forum https://software.intel.com/en-us/articles/intelr-memory-latency-checker

https://software.intel.com/en-us/forum

Allan.

topic Interpreting Intel Memory Latency Checker Output. in Mobile and Desktop Processors

Interpreting Intel Memory Latency Checker Output.

Re: Interpreting Intel Memory Latency Checker Output.