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    <title>topic Xeon memory bandwidth in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496478#M24569</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to understand the maximum (theoretical) memory bandwidth of Xeon processors so that our applications can maximize their bandwidth.  I thought I had it figured out, but now I have a processor where I don't understand how the maximum numbers make sense.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here's an example I think I understand:  Xeon E5-2630 v3 (Haswell-EP).  The maximum memory bandwidth (according to ARK) is 59 GB/s.  It has 4 memory channels and supports up to DDR4-1866 DIMMs.  The peak transfer rate of a DDR4-1866 DIMM is 14933 MB/s, and 14933 * 4 = 59732 MB/s, so this adds up.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What I don't understand: Xeon E7-4830 v3 (Haswell-EX).  The maximum memory bandwidth is 102 GB/s.  But it also supports up to DDR4-1866 and has 4 memory channels!  So how does it get 102 GB/s?  One theory is that the E7-4830 v3 has two memory controllers.  While cpu-world confirms this, it also says that each controller has 2 memory channels, so it still doesn't add up.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'd appreciate any help from the experts over here.  Is the number of memory controllers documented by Intel anywhere?  I couldn't find it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance!&lt;/P&gt;</description>
    <pubDate>Sun, 01 Jan 2017 12:11:03 GMT</pubDate>
    <dc:creator>TPtac</dc:creator>
    <dc:date>2017-01-01T12:11:03Z</dc:date>
    <item>
      <title>Xeon memory bandwidth</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496478#M24569</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to understand the maximum (theoretical) memory bandwidth of Xeon processors so that our applications can maximize their bandwidth.  I thought I had it figured out, but now I have a processor where I don't understand how the maximum numbers make sense.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here's an example I think I understand:  Xeon E5-2630 v3 (Haswell-EP).  The maximum memory bandwidth (according to ARK) is 59 GB/s.  It has 4 memory channels and supports up to DDR4-1866 DIMMs.  The peak transfer rate of a DDR4-1866 DIMM is 14933 MB/s, and 14933 * 4 = 59732 MB/s, so this adds up.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What I don't understand: Xeon E7-4830 v3 (Haswell-EX).  The maximum memory bandwidth is 102 GB/s.  But it also supports up to DDR4-1866 and has 4 memory channels!  So how does it get 102 GB/s?  One theory is that the E7-4830 v3 has two memory controllers.  While cpu-world confirms this, it also says that each controller has 2 memory channels, so it still doesn't add up.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'd appreciate any help from the experts over here.  Is the number of memory controllers documented by Intel anywhere?  I couldn't find it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance!&lt;/P&gt;</description>
      <pubDate>Sun, 01 Jan 2017 12:11:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496478#M24569</guid>
      <dc:creator>TPtac</dc:creator>
      <dc:date>2017-01-01T12:11:03Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon memory bandwidth</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496479#M24570</link>
      <description>&lt;P&gt;Hello  tptacek,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please let me review your inquiry, as soon as I have more information I will update the thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Amy.&lt;/P&gt;</description>
      <pubDate>Mon, 02 Jan 2017 22:32:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496479#M24570</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2017-01-02T22:32:46Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon memory bandwidth</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496480#M24571</link>
      <description>&lt;P&gt;/thread/109769 tptacek, I am still reviewing your case.&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Thank you for your patience.&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Amy.&lt;/P&gt;</description>
      <pubDate>Wed, 11 Jan 2017 21:58:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496480#M24571</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2017-01-11T21:58:55Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon memory bandwidth</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496481#M24572</link>
      <description>&lt;P&gt;The Xeon E7-4830 v3 has 4 memory buffers, each buffer has 2 channels = 8 channels / CPU.  Thus, 14933 * 8 = ~120 (minus overheads); giving you an effective 102 GB/s advertised on &lt;A href="http://ark.intel.com"&gt;ark.intel.com&lt;/A&gt;.  &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best publicly available collateral that I have found was from Anandtech on an older Ivy Bridge, but the principle is the same...  &lt;/P&gt;&lt;P&gt;&lt;A href="http://www.anandtech.com/show/7757/quad-ivy-brigde-ex-60-cores-120-threads/3"&gt;http://www.anandtech.com/show/7757/quad-ivy-brigde-ex-60-cores-120-threads/3&lt;/A&gt; Now with High Bandwidth Memory - The Intel Xeon E7 v2 Review: Quad Socket, Up to 60 Cores/120 Threads &lt;/P&gt;</description>
      <pubDate>Thu, 26 Jan 2017 02:36:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Xeon-memory-bandwidth/m-p/496481#M24572</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2017-01-26T02:36:25Z</dc:date>
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