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    <title>topic Re: access to required pages of instructions in pipeline in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593018#M32471</link>
    <description>&lt;P&gt;Hello &lt;B&gt; serpico&lt;/B&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Thank you for contacting the Intel community.&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Please see if the information at the following link works for you:&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;A href="https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge"&gt;https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge&lt;/A&gt; &lt;A href="https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge"&gt;https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge&lt;/A&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;You can also check here:&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf"&gt;https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf&lt;/A&gt; &lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf"&gt;https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf&lt;/A&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Page 2-15&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;I hope that helps.&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Regards,&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Ivan U.&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 05 Jun 2017 23:02:49 GMT</pubDate>
    <dc:creator>idata</dc:creator>
    <dc:date>2017-06-05T23:02:49Z</dc:date>
    <item>
      <title>access to required pages of instructions in pipeline</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593017#M32470</link>
      <description>&lt;P&gt;I do academic research and to test our ideas we need to answer these questions.&lt;/P&gt;&lt;P&gt;We wanted to see what instructions are actually in the CPU pipeline. I have looked in the related papers or CPU documentation and couldn't find any API or something that exposes a this functionality to higher abstractions like operating systems.&lt;/P&gt;&lt;P&gt;For instance, it might be possible to improve the paging algorithms in the operating systems if we are aware of the pages accessed by the instructions available in the pipeline for the future decisions.&lt;/P&gt;&lt;P&gt;And one of the key questions to this solution is whether we could access to the fetched instructions in the pipeline from the operating system or not. Probably it is not feasible or possible at all but it is really good if we could become sure of it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It would be awesome if we could have your comments on this issue&lt;/P&gt;</description>
      <pubDate>Mon, 05 Jun 2017 13:56:48 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593017#M32470</guid>
      <dc:creator>mrahm7</dc:creator>
      <dc:date>2017-06-05T13:56:48Z</dc:date>
    </item>
    <item>
      <title>Re: access to required pages of instructions in pipeline</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593018#M32471</link>
      <description>&lt;P&gt;Hello &lt;B&gt; serpico&lt;/B&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Thank you for contacting the Intel community.&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Please see if the information at the following link works for you:&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;A href="https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge"&gt;https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge&lt;/A&gt; &lt;A href="https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge"&gt;https://software.intel.com/en-us/blogs/2011/11/22/pipeline-speak-learning-more-about-intel-microarchitecture-codename-sandy-bridge&lt;/A&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;You can also check here:&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf"&gt;https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf&lt;/A&gt; &lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf"&gt;https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf&lt;/A&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Page 2-15&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;I hope that helps.&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Regards,&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt;Ivan U.&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 05 Jun 2017 23:02:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593018#M32471</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2017-06-05T23:02:49Z</dc:date>
    </item>
    <item>
      <title>Re: access to required pages of instructions in pipeline</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593019#M32472</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Hello ,&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;I'm following on this post to ask you if the information posted above solved your problem or if you need further assistance.&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Regards,&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Ivan.</description>
      <pubDate>Mon, 12 Jun 2017 18:25:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/access-to-required-pages-of-instructions-in-pipeline/m-p/593019#M32472</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2017-06-12T18:25:35Z</dc:date>
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