https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673782#M39676 <P>Wrong forum. Try <A href="https://forums.intel.com/s/topic/0TO0P000000MWKDWA4/fpga-soc-and-cpld-boards-and-kits">https://forums.intel.com/s/topic/0TO0P000000MWKDWA4/fpga-soc-and-cpld-boards-and-kits</A></P><P>&nbsp;</P><P>Doc</P><P>&nbsp;</P> Wed, 19 Feb 2020 13:38:27 GMT AlHill 2020-02-19T13:38:27Z https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673781#M39675 <P>Currently, I design the power distribution network for my customer. My customer uses intel stratix 10 mx. Then, I made some evaluation boards and&nbsp; measure some performance. As a results, the voltage fluctuation exceeds the limit. It's come from the anti-resonance peak of the PDN impedance. So I have to re-design the PDN. Could you tell me the on die capacitance of stratix 10 mx to decrease and re-design the PDN? </P> Wed, 19 Feb 2020 13:32:10 GMT https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673781#M39675 SHash6 2020-02-19T13:32:10Z https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673782#M39676 <P>Wrong forum. Try <A href="https://forums.intel.com/s/topic/0TO0P000000MWKDWA4/fpga-soc-and-cpld-boards-and-kits">https://forums.intel.com/s/topic/0TO0P000000MWKDWA4/fpga-soc-and-cpld-boards-and-kits</A></P><P>&nbsp;</P><P>Doc</P><P>&nbsp;</P> Wed, 19 Feb 2020 13:38:27 GMT https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673782#M39676 AlHill 2020-02-19T13:38:27Z https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673783#M39677 <P>Thank you.</P><P>I'll resubmit a post.</P> Wed, 19 Feb 2020 13:42:52 GMT https://community.intel.com/t5/Mobile-and-Desktop-Processors/On-die-capacitance/m-p/673783#M39677 SHash6 2020-02-19T13:42:52Z