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    <title>topic Possible Error in SDM 3 in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1191091#M45212</link>
    <description>&lt;P&gt;I think there might be a slight error in figures 2-1 and 2-2 of the Intel Software Development Manual Volume 3:&amp;nbsp;System Programming Guide.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;Figures 2-1 and 2-2 depict an overview of the System-Level Registers and Data Structures for IA-32 and IA-32e mode, respectively. At the top of the figure, there's a legend specifying that physical addresses are denoted by dotted-line arrows:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot 2020-07-07 at 14.40.25.png" style="width: 246px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/11126i377337C0AA10A1EE/image-size/large/is-moderation-mode/true?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Screenshot 2020-07-07 at 14.40.25.png" alt="Screenshot 2020-07-07 at 14.40.25.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;At the bottom of the figures, the data structures for the memory-management unit can be seen in an page mapping example.&lt;/P&gt;
&lt;P&gt;Given that the Page-Structure entries contain the physical address of the next-level page structure (or a mapped page frame, in the case of Page Table Entries), those arrows should be denoted by dashed-line arrows (Physical Address).&lt;/P&gt;
&lt;P&gt;See the following pictures:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Figure 2-2, highlighted arrows should be physical address arrows." style="width: 999px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/11128i954ABFF2B920E174/image-size/large/is-moderation-mode/true?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="ink (2).png" alt="Figure 2-2, highlighted arrows should be physical address arrows." /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Figure 2-2, highlighted arrows should be physical address arrows.&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Figure 2-1, highlighted arrows should be physical address arrows." style="width: 999px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/11129iCF1069BD72A2190A/image-size/large/is-moderation-mode/true?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="ink (1).png" alt="Figure 2-1, highlighted arrows should be physical address arrows." /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Figure 2-1, highlighted arrows should be physical address arrows.&lt;/span&gt;&lt;/span&gt;&lt;BR /&gt;The highlighted arrows should be of the same kind as the arrow that goes from the CR3 to the Page Directory or PML4 in figures 2-1 and 2-2 respectively.&lt;/P&gt;
&lt;P&gt;In chapter&amp;nbsp;&lt;SPAN&gt;4.2 "&lt;/SPAN&gt;&lt;SPAN&gt;HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW", it is mentioned that indeed, those entries contain physical addresses:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;"Each paging-structure entry contains a physical address, which is either the address of another paging structure or the address of a page frame. In the first case, the entry is said to reference the other paging structure; in the latter, the entry is said to map a page."&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 09 Jul 2020 20:03:00 GMT</pubDate>
    <dc:creator>charco</dc:creator>
    <dc:date>2020-07-09T20:03:00Z</dc:date>
    <item>
      <title>Possible Error in SDM 3</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1191091#M45212</link>
      <description>&lt;P&gt;I think there might be a slight error in figures 2-1 and 2-2 of the Intel Software Development Manual Volume 3:&amp;nbsp;System Programming Guide.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;Figures 2-1 and 2-2 depict an overview of the System-Level Registers and Data Structures for IA-32 and IA-32e mode, respectively. At the top of the figure, there's a legend specifying that physical addresses are denoted by dotted-line arrows:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot 2020-07-07 at 14.40.25.png" style="width: 246px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/11126i377337C0AA10A1EE/image-size/large/is-moderation-mode/true?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Screenshot 2020-07-07 at 14.40.25.png" alt="Screenshot 2020-07-07 at 14.40.25.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;At the bottom of the figures, the data structures for the memory-management unit can be seen in an page mapping example.&lt;/P&gt;
&lt;P&gt;Given that the Page-Structure entries contain the physical address of the next-level page structure (or a mapped page frame, in the case of Page Table Entries), those arrows should be denoted by dashed-line arrows (Physical Address).&lt;/P&gt;
&lt;P&gt;See the following pictures:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Figure 2-2, highlighted arrows should be physical address arrows." style="width: 999px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/11128i954ABFF2B920E174/image-size/large/is-moderation-mode/true?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="ink (2).png" alt="Figure 2-2, highlighted arrows should be physical address arrows." /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Figure 2-2, highlighted arrows should be physical address arrows.&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Figure 2-1, highlighted arrows should be physical address arrows." style="width: 999px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/11129iCF1069BD72A2190A/image-size/large/is-moderation-mode/true?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="ink (1).png" alt="Figure 2-1, highlighted arrows should be physical address arrows." /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Figure 2-1, highlighted arrows should be physical address arrows.&lt;/span&gt;&lt;/span&gt;&lt;BR /&gt;The highlighted arrows should be of the same kind as the arrow that goes from the CR3 to the Page Directory or PML4 in figures 2-1 and 2-2 respectively.&lt;/P&gt;
&lt;P&gt;In chapter&amp;nbsp;&lt;SPAN&gt;4.2 "&lt;/SPAN&gt;&lt;SPAN&gt;HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW", it is mentioned that indeed, those entries contain physical addresses:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;"Each paging-structure entry contains a physical address, which is either the address of another paging structure or the address of a page frame. In the first case, the entry is said to reference the other paging structure; in the latter, the entry is said to map a page."&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 09 Jul 2020 20:03:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1191091#M45212</guid>
      <dc:creator>charco</dc:creator>
      <dc:date>2020-07-09T20:03:00Z</dc:date>
    </item>
    <item>
      <title>Re:Possible Error in SDM 3</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1197017#M45244</link>
      <description>&lt;P&gt;charco, Thank you for posting in the Intel® Communities Support.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you very much also for providing those details, for this specific matter to be addressed, what we recommend is visit, sign-in and submit your comments in our Intel® Developer Zone of in our Intel® Resource and Design Center web sites:&lt;/P&gt;&lt;P&gt;&lt;A href="https://software.intel.com/content/www/us/en/develop/home.html" target="_blank"&gt;https://software.intel.com/content/www/us/en/develop/home.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/design/resource-design-center.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/design/resource-design-center.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Any questions, please let me know.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Albert R.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;A Contingent Worker at Intel&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 03 Aug 2020 19:41:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1197017#M45244</guid>
      <dc:creator>Alberto_Sykes</dc:creator>
      <dc:date>2020-08-03T19:41:49Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Possible Error in SDM 3</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1212333#M46430</link>
      <description>&lt;P&gt;Hi Albert,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you for your reply.&lt;/P&gt;
&lt;P&gt;Could you point me to where I should post the comments? I followed the links and tried to look for a place to post comments to, I get redirected to community.intel.com (this web page).&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Marco&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 24 Sep 2020 22:44:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Possible-Error-in-SDM-3/m-p/1212333#M46430</guid>
      <dc:creator>charco</dc:creator>
      <dc:date>2020-09-24T22:44:30Z</dc:date>
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