<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Cache replacement policy in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1255463#M49602</link>
    <description>HI, I’m a engineering student and I’m trying to get some information about de replacement policies in cache used on the Intel Core i7-9750H (I’m making a research about cache behavior on programs with a very poor spatial locality using this chipset) . The nearest information that I’ve found is that it is using something like LRU. I would like to know if it is using a private policy  so I can’t not get this kind of information and if it’s public I would like to know where I could learn more about it.   &lt;BR /&gt;Thanks.</description>
    <pubDate>Thu, 11 Feb 2021 23:35:12 GMT</pubDate>
    <dc:creator>Jabepi</dc:creator>
    <dc:date>2021-02-11T23:35:12Z</dc:date>
    <item>
      <title>Cache replacement policy</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1255463#M49602</link>
      <description>HI, I’m a engineering student and I’m trying to get some information about de replacement policies in cache used on the Intel Core i7-9750H (I’m making a research about cache behavior on programs with a very poor spatial locality using this chipset) . The nearest information that I’ve found is that it is using something like LRU. I would like to know if it is using a private policy  so I can’t not get this kind of information and if it’s public I would like to know where I could learn more about it.   &lt;BR /&gt;Thanks.</description>
      <pubDate>Thu, 11 Feb 2021 23:35:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1255463#M49602</guid>
      <dc:creator>Jabepi</dc:creator>
      <dc:date>2021-02-11T23:35:12Z</dc:date>
    </item>
    <item>
      <title>Re:Cache replacement policy</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1255730#M49619</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/151874"&gt;@Jabepi&lt;/a&gt;&lt;/P&gt;&lt;P&gt;Thank you for posting on the Intel® communities.&lt;/P&gt;&lt;P&gt;Please allow us to check this inquiry further. We will be posting back in the thread as soon as more details are available.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Andrew G.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 12 Feb 2021 22:18:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1255730#M49619</guid>
      <dc:creator>AndrewG_Intel</dc:creator>
      <dc:date>2021-02-12T22:18:46Z</dc:date>
    </item>
    <item>
      <title>Re:Cache replacement policy</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1256985#M49709</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/151874"&gt;@Jabepi&lt;/a&gt;&lt;/P&gt;&lt;P&gt;Thank you for your patience in this matter.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regarding your inquiry, we would like to inform you that Intel® processors are capable of implementing different cache replacement algorithms as required by a given application i.e. the instructions are available for implementation.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;You may go through the&amp;nbsp;&lt;A href="https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html" rel="noopener noreferrer" target="_blank"&gt;&lt;I&gt;Intel® 64 and IA-32 Architectures Software Developer Manuals&lt;/I&gt;&lt;/A&gt;&lt;I&gt;&amp;nbsp;&lt;/I&gt;specifically Chapter 11 on "&lt;I&gt;Memory Cache Control&lt;/I&gt;" to learn more about this.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For queries on software development, we recommend posting additional questions in the &lt;A href="https://community.intel.com/t5/Software-Development-Topics/ct-p/software-dev-topics" rel="noopener noreferrer" target="_blank"&gt;&lt;B&gt;Software Development Topics&lt;/B&gt;&lt;/A&gt; forums.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Andrew G.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 17 Feb 2021 22:55:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1256985#M49709</guid>
      <dc:creator>AndrewG_Intel</dc:creator>
      <dc:date>2021-02-17T22:55:29Z</dc:date>
    </item>
    <item>
      <title>Re:Cache replacement policy</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1258300#M49821</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/151874"&gt;@Jabepi&lt;/a&gt;&lt;/P&gt;&lt;P&gt;We have not heard back from you so we will proceed to close this thread now. If you need any additional information, please submit a new question as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Andrew G.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 22 Feb 2021 23:04:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Cache-replacement-policy/m-p/1258300#M49821</guid>
      <dc:creator>AndrewG_Intel</dc:creator>
      <dc:date>2021-02-22T23:04:22Z</dc:date>
    </item>
  </channel>
</rss>

