https://community.intel.com/t5/Mobile-and-Desktop-Processors/8085/m-p/1313569#M53477 <P>'DAD' instruction in 8085 works only with the HL pair. I just want to know that whether this instruction involves Accumulator in backend or not.&nbsp;</P> Fri, 10 Sep 2021 07:44:29 GMT shri 2021-09-10T07:44:29Z https://community.intel.com/t5/Mobile-and-Desktop-Processors/8085/m-p/1313569#M53477 <P>'DAD' instruction in 8085 works only with the HL pair. I just want to know that whether this instruction involves Accumulator in backend or not.&nbsp;</P> Fri, 10 Sep 2021 07:44:29 GMT https://community.intel.com/t5/Mobile-and-Desktop-Processors/8085/m-p/1313569#M53477 shri 2021-09-10T07:44:29Z https://community.intel.com/t5/Mobile-and-Desktop-Processors/8085/m-p/1313582#M53479 <P>Oh man, stress my aging brain cells. I haven't looked at this stuff in 40 years!</P> <P>DAD, Double Register Add, adds the contents of B&amp;C, D&amp;E, H&amp;L or SP to the contents of H&amp;L and places the result in H&amp;L. Forms are:</P> <TABLE> <TBODY> <TR> <TD>DAD</TD> <TD>B</TD> <TD>ADD</TD> <TD>HL,BC</TD> <TD>09</TD> <TD>HL &lt;- HL + BC</TD> </TR> <TR> <TD>DAD</TD> <TD>D</TD> <TD>ADD</TD> <TD>HL,DE</TD> <TD>19</TD> <TD>HL &lt;- HL + DE</TD> </TR> <TR> <TD>DAD</TD> <TD>H</TD> <TD>ADD</TD> <TD>HL,HL</TD> <TD>29</TD> <TD>HL &lt;- HL + HL</TD> </TR> <TR> <TD>DAD</TD> <TD>SP</TD> <TD>ADD</TD> <TD>HL,SP</TD> <TD>39</TD> <TD>HL &lt;- HL + SP</TD> </TR> </TBODY> </TABLE> <P>&nbsp;</P> <P>It can affect the Carry bit (CY), but I don't see it touching the Accumulator at all.</P> <P>...S</P> Fri, 10 Sep 2021 09:25:54 GMT https://community.intel.com/t5/Mobile-and-Desktop-Processors/8085/m-p/1313582#M53479 n_scott_pearson 2021-09-10T09:25:54Z