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    <title>topic Re:TLB information in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403955#M58826</link>
    <description>&lt;P&gt;Hello, FloR.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for marking the thread as resolved.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;It will be closed right now and no longer monitored by Intel support, but if you require any type of assistance from Intel in the future, you can always contact us back, just open a new thread or contact us via any of the available support methods.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Bruce C.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Wed, 27 Jul 2022 19:22:23 GMT</pubDate>
    <dc:creator>BrusC_Intel</dc:creator>
    <dc:date>2022-07-27T19:22:23Z</dc:date>
    <item>
      <title>TLB information</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1401478#M58745</link>
      <description>&lt;P&gt;Hi, where can I find information about the Translation Lookaside Buffers of Intel Xeon Gold 3rd Gen Processors. Does every model have the same TLB sizes per Core?&lt;/P&gt;</description>
      <pubDate>Tue, 19 Jul 2022 08:14:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1401478#M58745</guid>
      <dc:creator>FloR</dc:creator>
      <dc:date>2022-07-19T08:14:15Z</dc:date>
    </item>
    <item>
      <title>Re:TLB information</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1401641#M58750</link>
      <description>&lt;P&gt;Hello FloR,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;To continue with your request can you please provide the following:&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;1-Are you requesting this information on behalf of a company? If yes, please provide as many details as possible about the company that you work for. &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;2-Can you please let us know why you need this information? Is it for some sort of a project or for something else? Please provide as many details as possible.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Victor G. &lt;/P&gt;&lt;P&gt;Intel Technical Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 19 Jul 2022 18:27:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1401641#M58750</guid>
      <dc:creator>Victor_G_Intel</dc:creator>
      <dc:date>2022-07-19T18:27:17Z</dc:date>
    </item>
    <item>
      <title>Re: Re:TLB information</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1402546#M58784</link>
      <description>&lt;P&gt;Hi Victor,&lt;/P&gt;
&lt;P&gt;thanks for the quick response.&lt;/P&gt;
&lt;P&gt;I am a research assistant at the Systems Reasearch and Architectures Group at the University of Hannover, Germany [1].&lt;/P&gt;
&lt;P&gt;Our research activities include the exploration of new operating system abstractions for virtual memory. In this context, we have extended the Linux kernel to allow multiple address spaces in an operating system process; individual threads can switch between those address-spaces [2].&lt;BR /&gt;Since we generate more address-space switches with our kernel extension than usual, we are interested in the influence of the TLB properties.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Flo Rommel&lt;/P&gt;
&lt;P&gt;&amp;lt;removed&amp;gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Jul 2022 11:39:02 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1402546#M58784</guid>
      <dc:creator>FloR</dc:creator>
      <dc:date>2022-07-22T11:39:02Z</dc:date>
    </item>
    <item>
      <title>Re:TLB information</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403264#M58810</link>
      <description>&lt;P&gt;Hello, FloR.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Good day,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for the details provided.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We will review your request and I will contact you back in case additional information is required.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Bruce C.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 25 Jul 2022 22:23:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403264#M58810</guid>
      <dc:creator>BrusC_Intel</dc:creator>
      <dc:date>2022-07-25T22:23:28Z</dc:date>
    </item>
    <item>
      <title>Re:TLB information</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403538#M58814</link>
      <description>&lt;P&gt;Hello, FloR.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for waiting.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;I can confirm it is the same TLB size per core for all models, with a size per core of 2k for the Ice Lake (3rd Gen Xeon) and 1.5k for the Cascade Lake processors.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;There are some additional details here:&lt;/P&gt;&lt;P&gt;- &lt;A href="https://newsroom.intel.com/wp-content/uploads/sites/11/2021/04/3rd-Gen-Intel-Xeon-Scalable-Platform-Press-Presentation-281884.pdf" target="_blank"&gt;https://newsroom.intel.com/wp-content/uploads/sites/11/2021/04/3rd-Gen-Intel-Xeon-Scalable-Platform-Press-Presentation-281884.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;If you have other questions, or if I can help you with anything else, please let me know, and I will follow up on July 28th just in case.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Bruce C.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 26 Jul 2022 17:29:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403538#M58814</guid>
      <dc:creator>BrusC_Intel</dc:creator>
      <dc:date>2022-07-26T17:29:25Z</dc:date>
    </item>
    <item>
      <title>Re:TLB information</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403955#M58826</link>
      <description>&lt;P&gt;Hello, FloR.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for marking the thread as resolved.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;It will be closed right now and no longer monitored by Intel support, but if you require any type of assistance from Intel in the future, you can always contact us back, just open a new thread or contact us via any of the available support methods.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Bruce C.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 27 Jul 2022 19:22:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/TLB-information/m-p/1403955#M58826</guid>
      <dc:creator>BrusC_Intel</dc:creator>
      <dc:date>2022-07-27T19:22:23Z</dc:date>
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