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    <title>topic about PMEP(Persistent Memory Emulator Platform) in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/about-PMEP-Persistent-Memory-Emulator-Platform/m-p/297893#M6753</link>
    <description>&lt;P&gt;Hi. I am studying in Kookmin University Computer science(network system laboratory) in Seoul,Korea.&lt;/P&gt;&lt;P&gt;I read paper (System Software for Persistent Memory,Intel Labs,Intel Corp) that used PM Emulation Platform(PMEP).&lt;/P&gt;&lt;P&gt;it had this content.&lt;/P&gt;&lt;P&gt;PM Emulator System-level evaluation of PM software is&lt;/P&gt;&lt;P&gt;challenging due to lack of real hardware. Publicly available&lt;/P&gt;&lt;P&gt;simulators are either too slow and difficult to use with large&lt;/P&gt;&lt;P&gt;workloads [36] or too simplistic and unable to model the&lt;/P&gt;&lt;P&gt;effects of cache evictions, speculative execution, memorylevel&lt;/P&gt;&lt;P&gt;parallelism and prefetching in the CPU [10]. To enable&lt;/P&gt;&lt;P&gt;the performance study of PM software for a range of latency&lt;/P&gt;&lt;P&gt;and bandwidth points interesting to the emerging NVM technologies,&lt;/P&gt;&lt;P&gt;we built a PM performance emulator: PM Emulation&lt;/P&gt;&lt;P&gt;Platform (PMEP).&lt;/P&gt;&lt;P&gt;PMEP partitions the available DRAM memory into emulated&lt;/P&gt;&lt;P&gt;PM and regular volatile memory, emulates configurable&lt;/P&gt;&lt;P&gt;latencies and bandwidth for the PM range, allows&lt;/P&gt;&lt;P&gt;configuring pm wbarrier latency (default 100ns), and emulates&lt;/P&gt;&lt;P&gt;the optimized clflush operation.&lt;/P&gt;&lt;P&gt;PMEP is implemented on a dual-socket Intel R Xeon R&lt;/P&gt;&lt;P&gt;processor-based platform, using special CPU microcode and&lt;/P&gt;&lt;P&gt;custom platform firmware. Each processor runs at 2.6GHz,&lt;/P&gt;&lt;P&gt;has 8 cores, and supports up to 4 DDR3 Channels (with up to&lt;/P&gt;&lt;P&gt;2 DIMMs per Channel). The custom BIOS partitions available&lt;/P&gt;&lt;P&gt;memory such that channels 2-3 of each processor are&lt;/P&gt;&lt;P&gt;hidden from the OS and reserved for emulated PM. Channels&lt;/P&gt;&lt;P&gt;0-1 are used for regular DRAM. NUMA is disabled for PM&lt;/P&gt;&lt;P&gt;channels to ensure uniform access latencies. Unless specified&lt;/P&gt;&lt;P&gt;otherwise, PMEP has 16GB DRAM and 256GB PM, for&lt;/P&gt;&lt;P&gt;a 1:8 capacity ratio. Next we describe the details of PMEP&lt;/P&gt;&lt;P&gt;operation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to know pmep which is software or hardware. And I want to use pmep to study nonvolatile memory. How can i get pmep and pmep manual?&lt;/P&gt;&lt;P&gt;I attached this paper in mail.&lt;/P&gt;&lt;P&gt;Please see the attached file.&lt;/P&gt;&lt;P&gt;Thank you!!&lt;/P&gt;&lt;P&gt;  &lt;/P&gt;&lt;P&gt; I hope to get your reply soon. thank you&lt;/P&gt;</description>
    <pubDate>Thu, 25 Aug 2016 16:34:52 GMT</pubDate>
    <dc:creator>EEun</dc:creator>
    <dc:date>2016-08-25T16:34:52Z</dc:date>
    <item>
      <title>about PMEP(Persistent Memory Emulator Platform)</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/about-PMEP-Persistent-Memory-Emulator-Platform/m-p/297893#M6753</link>
      <description>&lt;P&gt;Hi. I am studying in Kookmin University Computer science(network system laboratory) in Seoul,Korea.&lt;/P&gt;&lt;P&gt;I read paper (System Software for Persistent Memory,Intel Labs,Intel Corp) that used PM Emulation Platform(PMEP).&lt;/P&gt;&lt;P&gt;it had this content.&lt;/P&gt;&lt;P&gt;PM Emulator System-level evaluation of PM software is&lt;/P&gt;&lt;P&gt;challenging due to lack of real hardware. Publicly available&lt;/P&gt;&lt;P&gt;simulators are either too slow and difficult to use with large&lt;/P&gt;&lt;P&gt;workloads [36] or too simplistic and unable to model the&lt;/P&gt;&lt;P&gt;effects of cache evictions, speculative execution, memorylevel&lt;/P&gt;&lt;P&gt;parallelism and prefetching in the CPU [10]. To enable&lt;/P&gt;&lt;P&gt;the performance study of PM software for a range of latency&lt;/P&gt;&lt;P&gt;and bandwidth points interesting to the emerging NVM technologies,&lt;/P&gt;&lt;P&gt;we built a PM performance emulator: PM Emulation&lt;/P&gt;&lt;P&gt;Platform (PMEP).&lt;/P&gt;&lt;P&gt;PMEP partitions the available DRAM memory into emulated&lt;/P&gt;&lt;P&gt;PM and regular volatile memory, emulates configurable&lt;/P&gt;&lt;P&gt;latencies and bandwidth for the PM range, allows&lt;/P&gt;&lt;P&gt;configuring pm wbarrier latency (default 100ns), and emulates&lt;/P&gt;&lt;P&gt;the optimized clflush operation.&lt;/P&gt;&lt;P&gt;PMEP is implemented on a dual-socket Intel R Xeon R&lt;/P&gt;&lt;P&gt;processor-based platform, using special CPU microcode and&lt;/P&gt;&lt;P&gt;custom platform firmware. Each processor runs at 2.6GHz,&lt;/P&gt;&lt;P&gt;has 8 cores, and supports up to 4 DDR3 Channels (with up to&lt;/P&gt;&lt;P&gt;2 DIMMs per Channel). The custom BIOS partitions available&lt;/P&gt;&lt;P&gt;memory such that channels 2-3 of each processor are&lt;/P&gt;&lt;P&gt;hidden from the OS and reserved for emulated PM. Channels&lt;/P&gt;&lt;P&gt;0-1 are used for regular DRAM. NUMA is disabled for PM&lt;/P&gt;&lt;P&gt;channels to ensure uniform access latencies. Unless specified&lt;/P&gt;&lt;P&gt;otherwise, PMEP has 16GB DRAM and 256GB PM, for&lt;/P&gt;&lt;P&gt;a 1:8 capacity ratio. Next we describe the details of PMEP&lt;/P&gt;&lt;P&gt;operation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to know pmep which is software or hardware. And I want to use pmep to study nonvolatile memory. How can i get pmep and pmep manual?&lt;/P&gt;&lt;P&gt;I attached this paper in mail.&lt;/P&gt;&lt;P&gt;Please see the attached file.&lt;/P&gt;&lt;P&gt;Thank you!!&lt;/P&gt;&lt;P&gt;  &lt;/P&gt;&lt;P&gt; I hope to get your reply soon. thank you&lt;/P&gt;</description>
      <pubDate>Thu, 25 Aug 2016 16:34:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/about-PMEP-Persistent-Memory-Emulator-Platform/m-p/297893#M6753</guid>
      <dc:creator>EEun</dc:creator>
      <dc:date>2016-08-25T16:34:52Z</dc:date>
    </item>
    <item>
      <title>Re: about PMEP(Persistent Memory Emulator Platform)</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/about-PMEP-Persistent-Memory-Emulator-Platform/m-p/297894#M6754</link>
      <description>&lt;P&gt;I have read the document you attached and I was trying to find the proper area of support, I would recommend addressing this matter through the SSD department. You can post this question at: &lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;/community/tech/solidstate &lt;A href="https://communities.intel.com/community/tech/solidstate"&gt;https://communities.intel.com/community/tech/solidstate&lt;/A&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Allan.</description>
      <pubDate>Fri, 26 Aug 2016 18:57:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/about-PMEP-Persistent-Memory-Emulator-Platform/m-p/297894#M6754</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2016-08-26T18:57:27Z</dc:date>
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