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    <title>topic Re:Intel N100  design issues in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1612825#M74207</link>
    <description>&lt;P&gt;Hello EfiGO,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for posting in Intel community Forum.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;For us to further check this, please help provide the following details:&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Why are you reporting this issue?&lt;/LI&gt;&lt;LI&gt;Are you having am issue with this processor?&lt;/LI&gt;&lt;LI&gt;Are you designing a board/system with this processor? &lt;/LI&gt;&lt;LI&gt;If yes, can you share more details about the design?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;If you have questions, please let us know. Thank you.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Mon, 08 Jul 2024 01:52:55 GMT</pubDate>
    <dc:creator>Mike_Intel</dc:creator>
    <dc:date>2024-07-08T01:52:55Z</dc:date>
    <item>
      <title>Intel N100  design issues</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1612258#M74103</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;My customer&amp;nbsp; have the design back from manufacturing. The design is very similar to the DDR5 CRB but they are counting on the VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05 to be supplied from the CPU FIVR.&lt;/P&gt;&lt;P&gt;For now they don't see that the processor is executing any BIOS code at all; although they see SPI flash transactions showing that the PCH at least is alive.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The question that they have for now is how configure the CPU Straps to use the CPU FIVR to supply VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please refer to the snippet from the schematics that processor CC34/CD34 are shorted and CA28/CC28 are shorted without being externally supplied.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EfiGO_0-1720098336694.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/56591iC1F3EE10B74A7E62/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="EfiGO_0-1720098336694.png" alt="EfiGO_0-1720098336694.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;they also got the Intel modular flash tool and they see how to configure VCCANA from FIVR; but we do not see how to do that for VCC_VNNEXT and VCC_V1P05EXT as below -&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EfiGO_1-1720098336705.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/56590iD8A31A381545E9BC/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="EfiGO_1-1720098336705.png" alt="EfiGO_1-1720098336705.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 04 Jul 2024 13:07:11 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1612258#M74103</guid>
      <dc:creator>EfiGO</dc:creator>
      <dc:date>2024-07-04T13:07:11Z</dc:date>
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    <item>
      <title>Re:Intel N100  design issues</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1612825#M74207</link>
      <description>&lt;P&gt;Hello EfiGO,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for posting in Intel community Forum.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;For us to further check this, please help provide the following details:&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Why are you reporting this issue?&lt;/LI&gt;&lt;LI&gt;Are you having am issue with this processor?&lt;/LI&gt;&lt;LI&gt;Are you designing a board/system with this processor? &lt;/LI&gt;&lt;LI&gt;If yes, can you share more details about the design?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;If you have questions, please let us know. Thank you.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 08 Jul 2024 01:52:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1612825#M74207</guid>
      <dc:creator>Mike_Intel</dc:creator>
      <dc:date>2024-07-08T01:52:55Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Intel N100  design issues</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1613855#M74315</link>
      <description>&lt;P&gt;Hi Mike,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for the response.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. Customer has a question which is more in detailed in the&amp;nbsp; above description:&amp;nbsp;&lt;/P&gt;&lt;P&gt;"The question that we have for now is how configure the CPU Straps to use the CPU FIVR to supply VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05?"&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp; Customer have finished the 1st design (SBC) and recieved it, they are not seeing CPU is conducting any BIOS code for now/ and they have the above question as well. they need some guidance from Intel team&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;3. Yes. SBC and a complete system&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;4. They have a project of 50K pcs from the N100 solution with some of their partners. on prem mini computer.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I need Intel help to move forward.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 10 Jul 2024 13:06:54 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1613855#M74315</guid>
      <dc:creator>EfiGO</dc:creator>
      <dc:date>2024-07-10T13:06:54Z</dc:date>
    </item>
    <item>
      <title>Re:Intel N100  design issues</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1613945#M74327</link>
      <description>&lt;P&gt;Hello EfiGO,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for the quick reply.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Upon checking, we recommend that you&amp;nbsp;should reach out to our&amp;nbsp;&lt;A href="https://www.intel.com/content/www/us/en/support/contact-intel.html#support-intel-programs" rel="noopener noreferrer" target="_blank"&gt;Developer Zone Support&amp;nbsp;&lt;/A&gt;or get in touch with a Field Application Engineer for specialized assistance. They are the best team who can assist you regarding this inquiry.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Also check this link on how to create an account:&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Since you will be contacting our Developer Zone, I need to close this inquiry.&amp;nbsp;&lt;/P&gt;&lt;P&gt;If you need further assistance, please post a new question as this thread will no longer be monitored.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you and have a great day.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 10 Jul 2024 20:32:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-N100-design-issues/m-p/1613945#M74327</guid>
      <dc:creator>Mike_Intel</dc:creator>
      <dc:date>2024-07-10T20:32:28Z</dc:date>
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