<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: computer architecture ( RISC vs CISC ) in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1667142#M81762</link>
    <description>&lt;P&gt;Modern processors are dramatically more powerful than the old RISC approach which was a cheaper CPU design. The RISC CPU used far less microcode to save on design cost.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;AMD64 which both Intel and AMD share also are dramatically richer in capabilities. Skylake is the 4th gen 64-bit architecture which is now going on since my Dell 3050 micro PC box with its i3-6100 CPU. I have pondered an i5 CPU to have 4 cores which gets rid of hyperthreading.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 18 Feb 2025 03:06:13 GMT</pubDate>
    <dc:creator>windows_guru</dc:creator>
    <dc:date>2025-02-18T03:06:13Z</dc:date>
    <item>
      <title>computer architecture ( RISC vs CISC )</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1666959#M81747</link>
      <description>&lt;P&gt;RISC : means reduced instruction ( more ) but each one is simple so its time complexity considered to be few compared to CISC&amp;nbsp; , so for eg. to perform the following exp. A=B+C&amp;nbsp; using :&amp;nbsp;&lt;/P&gt;&lt;P&gt;RISC pattern :&lt;/P&gt;&lt;P&gt;load R1 , B&amp;nbsp;&lt;/P&gt;&lt;P&gt;load R2 , C&lt;/P&gt;&lt;P&gt;add R3,R1,R2&lt;/P&gt;&lt;P&gt;store R3,A&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;==&amp;gt;(pseudocode)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;using : CISC&amp;nbsp;&lt;/P&gt;&lt;P&gt;directly :&lt;/P&gt;&lt;P&gt;add A,B,C&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;so the question is since both patterns gave the same output at the end b+c will be stored in a ,&amp;nbsp;&lt;/P&gt;&lt;P&gt;but the difference that # of used instructions , but why also the time complexity is not the same ( as I have mentioned above ( definition ) ) since add A,B,C will be simplified into simple instructions as in RISC ( this will happen implicitly for the dev. ) so the time must be the same ??&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;summary :&amp;nbsp;pseudocode of RISC ===&amp;nbsp;pseudocode of CISC , so the time at the end must be the same ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 17 Feb 2025 13:10:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1666959#M81747</guid>
      <dc:creator>Raya_R</dc:creator>
      <dc:date>2025-02-17T13:10:24Z</dc:date>
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    <item>
      <title>Re: computer architecture ( RISC vs CISC )</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1666963#M81748</link>
      <description>&lt;P&gt;What is your point?&amp;nbsp; Thirty years ago, this would have been an interesting discussion.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Doc (not an Intel employee or contractor)&lt;BR /&gt;[W10 is today's XP ]&lt;/P&gt;</description>
      <pubDate>Mon, 17 Feb 2025 13:19:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1666963#M81748</guid>
      <dc:creator>AlHill</dc:creator>
      <dc:date>2025-02-17T13:19:25Z</dc:date>
    </item>
    <item>
      <title>Re: computer architecture ( RISC vs CISC )</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1666973#M81749</link>
      <description>&lt;P&gt;my question is : why we say that the time complexity in RISC is fewer than in CISC , since at CISC the complicated instruction at the end will be simplified into simple instructions as the ones in RISC ?&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 17 Feb 2025 14:28:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1666973#M81749</guid>
      <dc:creator>Raya_R</dc:creator>
      <dc:date>2025-02-17T14:28:05Z</dc:date>
    </item>
    <item>
      <title>Re: computer architecture ( RISC vs CISC )</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1667011#M81752</link>
      <description>&lt;P&gt;Not a question that will be answered here.&amp;nbsp; This is a technical support forum for Intel products.&lt;/P&gt;&lt;P&gt;You can take your academic question back to the classroom and ask the instructor.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Doc (not an Intel employee or contractor)&lt;BR /&gt;[W10 is today's XP ]&lt;/P&gt;</description>
      <pubDate>Mon, 17 Feb 2025 17:07:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1667011#M81752</guid>
      <dc:creator>AlHill</dc:creator>
      <dc:date>2025-02-17T17:07:12Z</dc:date>
    </item>
    <item>
      <title>Re: computer architecture ( RISC vs CISC )</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1667142#M81762</link>
      <description>&lt;P&gt;Modern processors are dramatically more powerful than the old RISC approach which was a cheaper CPU design. The RISC CPU used far less microcode to save on design cost.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;AMD64 which both Intel and AMD share also are dramatically richer in capabilities. Skylake is the 4th gen 64-bit architecture which is now going on since my Dell 3050 micro PC box with its i3-6100 CPU. I have pondered an i5 CPU to have 4 cores which gets rid of hyperthreading.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 18 Feb 2025 03:06:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/computer-architecture-RISC-vs-CISC/m-p/1667142#M81762</guid>
      <dc:creator>windows_guru</dc:creator>
      <dc:date>2025-02-18T03:06:13Z</dc:date>
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  </channel>
</rss>

