<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic CPU confused specs in Mobile and Desktop Processors</title>
    <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674275#M82428</link>
    <description>I have a confusion about Intel i5 12400f desktop CPU .&lt;BR /&gt;Official Website says it has max 20 pcie lanes. And pcie configurations are 1x16+4, 2x8+4. So is this 4 lanes for chipset reservation or for SSD? I am confused. Can any expert here help me resolve my confusion?</description>
    <pubDate>Wed, 12 Mar 2025 01:35:29 GMT</pubDate>
    <dc:creator>H784</dc:creator>
    <dc:date>2025-03-12T01:35:29Z</dc:date>
    <item>
      <title>CPU confused specs</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674275#M82428</link>
      <description>I have a confusion about Intel i5 12400f desktop CPU .&lt;BR /&gt;Official Website says it has max 20 pcie lanes. And pcie configurations are 1x16+4, 2x8+4. So is this 4 lanes for chipset reservation or for SSD? I am confused. Can any expert here help me resolve my confusion?</description>
      <pubDate>Wed, 12 Mar 2025 01:35:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674275#M82428</guid>
      <dc:creator>H784</dc:creator>
      <dc:date>2025-03-12T01:35:29Z</dc:date>
    </item>
    <item>
      <title>Re: CPU confused specs</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674304#M82436</link>
      <description>Yes, those 4 PCIe lanes are typically used for a NVMe SSD. This will be the highest performing NVMe SSD interface; the others are supported by PCIe lanes generated by the chipset (PCH component), which all share access to the processor over the DMI bus.&lt;BR /&gt;...S</description>
      <pubDate>Wed, 12 Mar 2025 03:31:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674304#M82436</guid>
      <dc:creator>n_scott_pearson</dc:creator>
      <dc:date>2025-03-12T03:31:56Z</dc:date>
    </item>
    <item>
      <title>Re: CPU confused specs</title>
      <link>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674345#M82440</link>
      <description>If I had a GPU which requires 16 lane and and nvme ssd which requires 4 lane , if GPU and SSD possess 16 + 4 lane , where are the reserved CPU pcle lanes for chipset ? If I ain't wrong, 4 CPU pcie lane is reserved for chipset and&lt;BR /&gt;they will share brandwdith between them.</description>
      <pubDate>Wed, 12 Mar 2025 05:41:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Mobile-and-Desktop-Processors/CPU-confused-specs/m-p/1674345#M82440</guid>
      <dc:creator>H784</dc:creator>
      <dc:date>2025-03-12T05:41:34Z</dc:date>
    </item>
  </channel>
</rss>

