topic Basic VHDL arithmetic not working on std_logic_vectors in Altera (vs Xilinx) in Programmable Devices
https://community.intel.com/t5/Programmable-Devices/Basic-VHDL-arithmetic-not-working-on-std-logic-vectors-in-Altera/m-p/688618#M73660
<P>I am porting code that works on a Xilinx FPGA to an Altera FPGA. In my code, I use basic arithmetic operations on std_logic_vectors. As an example, I define the following libraries in my VHDL file:</P><P> </P><P>library IEEE;</P><P>use IEEE.STD_LOGIC_1164.ALL;</P><P>use IEEE.STD_LOGIC_ARITH.ALL;</P><P>use IEEE.STD_LOGIC_UNSIGNED.ALL;</P><P>use IEEE.NUMERIC_STD.ALL;</P><P> </P><P>Then if I define a signal:</P><P> </P><P>signal my_signal : std_logic_vector(4 downto 0);</P><P> </P><P>And then have a statement:</P><P>my_signal <= my_signal - 1;</P><P> </P><P>On the FPGA, this statement seems to be impacting only bit 0 of my_signal instead of the entire vector. I've tried to rewrite the statement as:</P><P> </P><P>my_signal <= std_logic_vector(unsigned(my_signal) - 1);</P><P> </P><P>but that is throwing off errors when I try to build the project. </P><P> </P><P>In Xilinx FPGA, the above statement works just fine, counting down the std_logic_vector (and turning over to 0b11111 when I subtract 1 from 0b00000). Why is this not working on the Intel/Altera FPGA?</P><P> </P><P> </P><P> </P>Fri, 12 Jul 2019 01:02:32 GMTEPrec2019-07-12T01:02:32ZBasic VHDL arithmetic not working on std_logic_vectors in Altera (vs Xilinx)
https://community.intel.com/t5/Programmable-Devices/Basic-VHDL-arithmetic-not-working-on-std-logic-vectors-in-Altera/m-p/688618#M73660
<P>I am porting code that works on a Xilinx FPGA to an Altera FPGA. In my code, I use basic arithmetic operations on std_logic_vectors. As an example, I define the following libraries in my VHDL file:</P><P> </P><P>library IEEE;</P><P>use IEEE.STD_LOGIC_1164.ALL;</P><P>use IEEE.STD_LOGIC_ARITH.ALL;</P><P>use IEEE.STD_LOGIC_UNSIGNED.ALL;</P><P>use IEEE.NUMERIC_STD.ALL;</P><P> </P><P>Then if I define a signal:</P><P> </P><P>signal my_signal : std_logic_vector(4 downto 0);</P><P> </P><P>And then have a statement:</P><P>my_signal <= my_signal - 1;</P><P> </P><P>On the FPGA, this statement seems to be impacting only bit 0 of my_signal instead of the entire vector. I've tried to rewrite the statement as:</P><P> </P><P>my_signal <= std_logic_vector(unsigned(my_signal) - 1);</P><P> </P><P>but that is throwing off errors when I try to build the project. </P><P> </P><P>In Xilinx FPGA, the above statement works just fine, counting down the std_logic_vector (and turning over to 0b11111 when I subtract 1 from 0b00000). Why is this not working on the Intel/Altera FPGA?</P><P> </P><P> </P><P> </P>Fri, 12 Jul 2019 01:02:32 GMThttps://community.intel.com/t5/Programmable-Devices/Basic-VHDL-arithmetic-not-working-on-std-logic-vectors-in-Altera/m-p/688618#M73660EPrec2019-07-12T01:02:32Z