topic Re: What is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab? in IntelÂ® QuartusÂ® Prime Software
https://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115663#M24851
<P>Thanks very much, dave_59. </P><P></P> <P></P>Actually, I am not clear what the assert statement it is. <P></P> <P></P>Is the assert statement like an assertion of reset? Could you please take an example to briefly describe what assert statement is? Thanks so much.Mon, 29 Apr 2013 23:14:43 GMTAltera_Forum2013-04-29T23:14:43ZWhat is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab?
https://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115661#M24849
<P>When I do simulation in Modelsim, in sim tab, there are "Assertion misses" and "Assertion hits", I attached a screenshot to show it, what is the mean of this? </P><P></P> <P></P>Thanks in advance.Mon, 29 Apr 2013 09:26:41 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115661#M24849Altera_Forum2013-04-29T09:26:41ZRe: What is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab?
https://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115662#M24850
<P>In VHDL, an assertion hit is an assert statement that did not fail. A miss is an assert statement that failed at least once. The words <B>pass </B>and <B>fail </B>are not used because in other languages, it possible to have the assertion pass, but still not considered a hit. (a vacuous pass) And an assertion that does not ever execute can be a miss.</P>Mon, 29 Apr 2013 23:09:45 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115662#M24850Altera_Forum2013-04-29T23:09:45ZRe: What is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab?
https://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115663#M24851
<P>Thanks very much, dave_59. </P><P></P> <P></P>Actually, I am not clear what the assert statement it is. <P></P> <P></P>Is the assert statement like an assertion of reset? Could you please take an example to briefly describe what assert statement is? Thanks so much.Mon, 29 Apr 2013 23:14:43 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115663#M24851Altera_Forum2013-04-29T23:14:43ZRe: What is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab?
https://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115664#M24852
<P><A href="http://vhdl.renerta.com/source/vhd00007.htm">http://vhdl.renerta.com/source/vhd00007.htm</A></P>Mon, 29 Apr 2013 23:26:31 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/What-is-the-mean-of-quot-Assertion-misses-quot-and-quot/m-p/115664#M24852Altera_Forum2013-04-29T23:26:31Z