topic Re: Maths Error in IntelÂ® QuartusÂ® Prime Software
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209953#M66244
<P>Why not do a fully synchronous design with all the registers clocked on <STRONG>posedge clk</STRONG> ?</P>
<P>Create an enable signal for the data processing block and include all the logic inside that block within it:</P>
<P><STRONG>always @ (posedge clk) begin</STRONG><BR /><STRONG> if (enable_enc) begin</STRONG><BR /><STRONG> ... do stuff ...</STRONG><BR /><STRONG> end</STRONG><BR /><STRONG>end</STRONG></P>
<P> </P>Wed, 16 Sep 2020 19:53:31 GMTak6dn2020-09-16T19:53:31ZMaths Error
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209855#M66242
<P>I have a block that is occasionally giving an error. I'm fairly sure it is due to timing, but I do not understand the problem.<BR /><BR />The following are relevant snippets.</P>
<P> </P>
<P> </P>
<LI-CODE lang="markup">reg enc_reg;
reg [31:0] enc_real_fast_time;
reg [31:0] enc_real_fast_time_prev;
reg [31:0] enc_pulse_period;
always @ (posedge clk) begin
enc_reg <= enc;
end
always @ (negedge enc_reg) begin
enc_pulse_period <= (fast_now - enc_real_fast_time_prev) / (divider*2);
enc_real_fast_time_prev <= enc_real_fast_time;
enc_real_fast_time <= fast_now;
end</LI-CODE>
<P> </P>
<P> </P>
<P> <BR />clk: A 50MHz output of a PLL block.<BR />enc: The input from an encoder. A synchronous approximately 20kHz.<BR />fast_now: A 32-bit count of clk, incremented on negative edges.<BR />divider: constant = 5.<BR /><BR />This usually works and results in enc_pulse_period of 496 (give or take one or two).<BR /><BR />Every few seconds, the result is wrong, either in the order of 400 or very large. It always (usually) occurs when fast_now is XXXX0000 at the time of the negedge enc_reg block.</P>
<P>My assumption is that the subtraction and division is occurring as the other values are changing and therefore gets incorrect bits in its calculation. I have tried using blocking assignments but that makes no difference.<BR /><BR />What am I doing wrong?<BR />What is best practice for making the enc_pulse_period reliably correct?<BR /><BR />This is an example of an error occurring.<BR /><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="enc_pulse_period.png" style="width: 999px;"><img src="https://community.intel.com/t5/image/serverpage/image-id/12715iA1B04EBD3ABC82A0/image-size/large?v=1.0&px=999" role="button" title="enc_pulse_period.png" alt="enc_pulse_period.png" /></span><BR />n.b. 8E800000h - 8E7F3C98h = 4968(d) -> 496 expected. [divider = 5]<BR /><BR /></P>Wed, 16 Sep 2020 13:49:38 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209855#M66242DBarn222020-09-16T13:49:38ZRe: Maths Error
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209861#M66243
<P>I tried a different solution...</P>
<LI-CODE lang="none">always @ (negedge enc_reg) begin
enc_real_fast_time_prev <= enc_real_fast_time;
enc_real_fast_time <= fast_now;
end
wire [31:0] enc_pulse_period;
assign enc_pulse_period = (enc_real_fast_time - enc_real_fast_time_prev) / divider;</LI-CODE>
<P>(Currently not quite the same functionality as it divides over one rather than two periods, but that is just detail).<BR /><BR />What this has shown is that the division takes many clock cycles to perform. Therein lies my problem.<BR /><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="enc_pulse_period2.png" style="width: 999px;"><img src="https://community.intel.com/t5/image/serverpage/image-id/12716iF36571271C5414CA/image-size/large?v=1.0&px=999" role="button" title="enc_pulse_period2.png" alt="enc_pulse_period2.png" /></span><BR /><BR />This may be a sufficient solution for what I need. I would still be interested to know if it is possible to do what I was initially trying to do.</P>Wed, 16 Sep 2020 14:05:51 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209861#M66243DBarn222020-09-16T14:05:51ZRe: Maths Error
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209953#M66244
<P>Why not do a fully synchronous design with all the registers clocked on <STRONG>posedge clk</STRONG> ?</P>
<P>Create an enable signal for the data processing block and include all the logic inside that block within it:</P>
<P><STRONG>always @ (posedge clk) begin</STRONG><BR /><STRONG> if (enable_enc) begin</STRONG><BR /><STRONG> ... do stuff ...</STRONG><BR /><STRONG> end</STRONG><BR /><STRONG>end</STRONG></P>
<P> </P>Wed, 16 Sep 2020 19:53:31 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209953#M66244ak6dn2020-09-16T19:53:31ZRe: Maths Error
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209961#M66246
<P>Two questions.</P>
<P> </P>
<P>Why would that work when my solution does not?</P>
<P>What is best practice for implementing enable_enc?</P>Wed, 16 Sep 2020 20:13:32 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209961#M66246DBarn222020-09-16T20:13:32ZRe: Maths Error
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209965#M66247
<P>Using a single synchronous clock with optional register enable(s) is simpler for Quartus to meet timing than deriving a bunch of signals that will be used as clocks. FPGAs only have a limited number of low skew, high drive clock layout resources.</P>
<P>As to implementing the enable signal, that is just some simple logic driving a register to create a one clock width pulse at the posedge clk when you want the logic to trigger. No special techniques needed.</P>Wed, 16 Sep 2020 20:34:03 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Maths-Error/m-p/1209965#M66247ak6dn2020-09-16T20:34:03Z