topic Constraints for Multiplexed Clocks in Intel® Quartus® Prime Software
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9676#M887
<P>I have an Arria V design that has 4 clocks: </P><P></P> <P></P>base_clk : from device pin to PLL input <P></P>clk_1x : 1x output from PLL (same frequency as base_clk) <P></P>clk_2x : 2x output from PLL (twice frequency of base_clk) <P></P>clk_mux : output of a 2:1 mux whose inputs are clk_1x and clk_2x <P></P> <P></P>I can't see to determine how to setup the .sdc constraints for these clocks to meet these requirements: <P></P> <P></P>1) there is logic on clk_1x, clk_2x, and clk_mux that assumes all of these clocks are synchronous to each other <P></P>2) the clk_mux is mode-based configured (i.e. the mux selection control is constant for a given operating mode) <P></P> <P></P>I have these basic lines in the .sdc file: <P></P> <P></P>create_clock -name base_clk -period 13.42 [get_nets {base_clk}] <P></P>derive_pll_clocks <P></P>derive_clock_uncertainty <P></P> <P></P>These constraints seem to take care of clk_1x and clk_2x domains but I can't figure out how to constrain clk_mux (assuming one is needed). <P></P> <P></P>I looked at the set_clock_groups documentation but I don't think I can use that because it would false path all nets between clk_1x and clk_2x (at least as I understand how the command works). <P></P> <P></P>Can someone help with this problem?Wed, 26 Jul 2017 04:01:58 GMTAltera_Forum2017-07-26T04:01:58ZConstraints for Multiplexed Clocks
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9676#M887
<P>I have an Arria V design that has 4 clocks: </P><P></P> <P></P>base_clk : from device pin to PLL input <P></P>clk_1x : 1x output from PLL (same frequency as base_clk) <P></P>clk_2x : 2x output from PLL (twice frequency of base_clk) <P></P>clk_mux : output of a 2:1 mux whose inputs are clk_1x and clk_2x <P></P> <P></P>I can't see to determine how to setup the .sdc constraints for these clocks to meet these requirements: <P></P> <P></P>1) there is logic on clk_1x, clk_2x, and clk_mux that assumes all of these clocks are synchronous to each other <P></P>2) the clk_mux is mode-based configured (i.e. the mux selection control is constant for a given operating mode) <P></P> <P></P>I have these basic lines in the .sdc file: <P></P> <P></P>create_clock -name base_clk -period 13.42 [get_nets {base_clk}] <P></P>derive_pll_clocks <P></P>derive_clock_uncertainty <P></P> <P></P>These constraints seem to take care of clk_1x and clk_2x domains but I can't figure out how to constrain clk_mux (assuming one is needed). <P></P> <P></P>I looked at the set_clock_groups documentation but I don't think I can use that because it would false path all nets between clk_1x and clk_2x (at least as I understand how the command works). <P></P> <P></P>Can someone help with this problem?Wed, 26 Jul 2017 04:01:58 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9676#M887Altera_Forum2017-07-26T04:01:58ZRe: Constraints for Multiplexed Clocks
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9677#M888
<P>I'm not sure why you're using get_nets. You should be pointing to the input port for the base clock: </P><P></P> <P></P>create_clock -name base_clk -period 13.42 [get_ports {base_clk}] <P></P> <P></P>You also probably need to make clk_mux a generated clock. It might even need to be two generated clocks, clk_mux_1x and clk_mux_2x, if the output of the mux is used as the source or destination clock and clk_1x or clk_2x are used at the other end. In other words, you need to think of all possibilities that you are using for the source and destination clocks throughout your design. <P></P> <P></P>As for your question, if all possibilities of source and destination clock are valid throughout your design (1x -> 2x, 2x -> 1x, 1x -> 1x, 2x -> 2x), then you don't need any false paths or clock group timing exceptions. Those are only needed when clock crossings in either direction between 1x and 2x should not be analyzed. What you do need, if you don't use separate registers to handle the transfers between the 1x and 2x clock domains, are multicycle timing exceptions. For going from 2x to 1x, you'll need start multicycle to move the launch edge and for going from 1x to 2x you may need end multicycle to move the latch edge used in the 2x domain to match up with the 1x domain. So it might look like this: <P></P> <P></P>set_multicycle_path –from clk_2x –to clk_1x –setup –start 2 <P></P>set_multicycle_path –from clk_2x –to clk_1x –hold –start 1 <P></P>set_multicycle_path –from clk_1x –to clk_2x –setup –end 2 <P></P>set_multicycle_path –from clk_1x –to clk_2x –hold –end 1 <P></P> <P></P>This Wiki page gives a good rundown of multicycle: <P></P> <P></P><A href="http://www.alterawiki.com/wiki/timing_constraints">http://www.alterawiki.com/wiki/timing_constraints</A>Wed, 26 Jul 2017 05:23:53 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9677#M888Altera_Forum2017-07-26T05:23:53ZRe: Constraints for Multiplexed Clocks
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9678#M889
<P>Yes, the "get_nets" should have been "get_ports" for my example (unfortunate typo). </P><P></P> <P></P>Your suggestions make sense and I will try to implement these in my next build and TimeQuest runs. <P></P> <P></P>Thanks for your help!Thu, 27 Jul 2017 02:31:50 GMThttps://community.intel.com/t5/Intel-Quartus-Prime-Software/Constraints-for-Multiplexed-Clocks/m-p/9678#M889Altera_Forum2017-07-27T02:31:50Z