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    <title>topic Re: How is Source Address Decoder programmed in a NUMA server? in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640965#M17609</link>
    <description>&lt;P&gt;Hello MBloo4,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We are following your question and would like to know if you need further assistance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Sergio S.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;Under Contract to Intel Corporation&lt;/P&gt;&lt;P&gt;For firmware updates and troubleshooting tips, visit :&lt;A href="https://intel.com/support/serverbios" target="_self" alt="https://intel.com/support/serverbios"&gt;&lt;/A&gt;&lt;A href="https://intel.com/support/serverbios"&gt;https://intel.com/support/serverbios&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 08 Aug 2019 08:30:24 GMT</pubDate>
    <dc:creator>SergioS_Intel</dc:creator>
    <dc:date>2019-08-08T08:30:24Z</dc:date>
    <item>
      <title>How is Source Address Decoder programmed in a NUMA server?</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640963#M17607</link>
      <description>&lt;P&gt;For things like hot-plugging of new QPI/UPI segments (e.g. populating a new CPU socket ) or of new DIMMs an attention button is used to invoke the SMM handler and reconfigure the SAD and the TAD in each node.  &lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But if the &lt;B&gt;OS remaps a PCI device&lt;/B&gt; (e.g. changing the value of one of its BARs) attached to a socket's &lt;B&gt;local PCIe link&lt;/B&gt;, it can potentially use an address &lt;B&gt;not routed to that socket&lt;/B&gt; by the current SAD configuration.  &lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;How is this case handled? How is the physical address space mapped between sockets (particularly, the part not backed by the RAM)?&lt;/P&gt;</description>
      <pubDate>Thu, 01 Aug 2019 22:30:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640963#M17607</guid>
      <dc:creator>MBloo4</dc:creator>
      <dc:date>2019-08-01T22:30:30Z</dc:date>
    </item>
    <item>
      <title>Re: How is Source Address Decoder programmed in a NUMA server?</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640964#M17608</link>
      <description>&lt;P&gt;Hello MBloo4,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please provide to us the model of your Intel(R) server board?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Sergio S.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;Under Contract to Intel Corporation&lt;/P&gt;&lt;P&gt;For firmware updates and troubleshooting tips, visit :&lt;A href="https://intel.com/support/serverbios"&gt;https://intel.com/support/serverbios&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 02 Aug 2019 07:56:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640964#M17608</guid>
      <dc:creator>SergioS_Intel</dc:creator>
      <dc:date>2019-08-02T07:56:37Z</dc:date>
    </item>
    <item>
      <title>Re: How is Source Address Decoder programmed in a NUMA server?</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640965#M17609</link>
      <description>&lt;P&gt;Hello MBloo4,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We are following your question and would like to know if you need further assistance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Sergio S.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;Under Contract to Intel Corporation&lt;/P&gt;&lt;P&gt;For firmware updates and troubleshooting tips, visit :&lt;A href="https://intel.com/support/serverbios" target="_self" alt="https://intel.com/support/serverbios"&gt;&lt;/A&gt;&lt;A href="https://intel.com/support/serverbios"&gt;https://intel.com/support/serverbios&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Aug 2019 08:30:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640965#M17609</guid>
      <dc:creator>SergioS_Intel</dc:creator>
      <dc:date>2019-08-08T08:30:24Z</dc:date>
    </item>
    <item>
      <title>Re: How is Source Address Decoder programmed in a NUMA server?</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640966#M17610</link>
      <description>&lt;P&gt;Hello MBloo4,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In case you need more help, please contact us back.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Sergio S.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;Under Contract to Intel Corporation&lt;/P&gt;&lt;P&gt;For firmware updates and troubleshooting tips, visit :&lt;A href="https://intel.com/support/serverbios" target="_self" alt="https://intel.com/support/serverbios"&gt;&lt;/A&gt;&lt;A href="https://intel.com/support/serverbios"&gt;https://intel.com/support/serverbios&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Aug 2019 06:10:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/How-is-Source-Address-Decoder-programmed-in-a-NUMA-server/m-p/640966#M17610</guid>
      <dc:creator>SergioS_Intel</dc:creator>
      <dc:date>2019-08-13T06:10:18Z</dc:date>
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