<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Eaglelake will be here soon... in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Eaglelake-will-be-here-soon/m-p/235246#M1794</link>
    <description>&lt;P&gt;Intel is releasing Eaglelake in Q2, next generation chipset set to replace Bearlake. Eaglelake will be available in two versions: Eaglelake-P and Eaglelake-G. The -G version will have integrated graphics and the -P version of the chipset will not. The chipset will support dual-core Wolfdale and quad-core Yorkfield processors, built on the 45nm manufacturing process, with a 1333MHz FSB, and PCI-Express 2.0. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unlike Bearlake, where only one of the derivatives will have PCI-Express 2.0 support, the X38 chipset, Eaglelake in both versions will support this feature, bringing the speed up to 5GT/Link, as opposed to 2.5GT/Link, the maximum currently supported bandwidth. The memory controller on Eaglelake will support DDR3-1333, with an expected support for DDR2-800.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Eaglelake will have many features such as display Port, HDMI, DVI, and HDCP, in addition to Clear Video engine HD-DVD and Blu-ray support. CPU bottlenecking will be alleviated with the help of Bitstream Processing/Entropy Decode, Frequency Transform, Pixel Prediction and Deblocking features. Also a new southbridge is in included, ICH10 for Eaglelake, which will do away with PS/2 and LPT ports, but will include a 10Gbit Ethernet controller, Wireless Ethernet controller and refined power consumption.&lt;/P&gt;</description>
    <pubDate>Tue, 20 May 2008 17:18:16 GMT</pubDate>
    <dc:creator>idata</dc:creator>
    <dc:date>2008-05-20T17:18:16Z</dc:date>
    <item>
      <title>Eaglelake will be here soon...</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Eaglelake-will-be-here-soon/m-p/235246#M1794</link>
      <description>&lt;P&gt;Intel is releasing Eaglelake in Q2, next generation chipset set to replace Bearlake. Eaglelake will be available in two versions: Eaglelake-P and Eaglelake-G. The -G version will have integrated graphics and the -P version of the chipset will not. The chipset will support dual-core Wolfdale and quad-core Yorkfield processors, built on the 45nm manufacturing process, with a 1333MHz FSB, and PCI-Express 2.0. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unlike Bearlake, where only one of the derivatives will have PCI-Express 2.0 support, the X38 chipset, Eaglelake in both versions will support this feature, bringing the speed up to 5GT/Link, as opposed to 2.5GT/Link, the maximum currently supported bandwidth. The memory controller on Eaglelake will support DDR3-1333, with an expected support for DDR2-800.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Eaglelake will have many features such as display Port, HDMI, DVI, and HDCP, in addition to Clear Video engine HD-DVD and Blu-ray support. CPU bottlenecking will be alleviated with the help of Bitstream Processing/Entropy Decode, Frequency Transform, Pixel Prediction and Deblocking features. Also a new southbridge is in included, ICH10 for Eaglelake, which will do away with PS/2 and LPT ports, but will include a 10Gbit Ethernet controller, Wireless Ethernet controller and refined power consumption.&lt;/P&gt;</description>
      <pubDate>Tue, 20 May 2008 17:18:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Eaglelake-will-be-here-soon/m-p/235246#M1794</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2008-05-20T17:18:16Z</dc:date>
    </item>
  </channel>
</rss>

