<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic how to use IP in OPAE in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256161#M20413</link>
    <description>&lt;P&gt;In github repo "intel_fpga_bbb", there are several samples for us to refer. However, I do not find any examples containing IP. So, what should we do if we want to use IP in our project?&lt;/P&gt;
&lt;P&gt;From my perspective, what we should do is generate IP with Quartus Prime Pro and mv to "rtl/avalon" directory. But how should we modify sources.txt file, which records the source code of the project.&lt;/P&gt;</description>
    <pubDate>Mon, 15 Feb 2021 20:26:30 GMT</pubDate>
    <dc:creator>yiheng</dc:creator>
    <dc:date>2021-02-15T20:26:30Z</dc:date>
    <item>
      <title>how to use IP in OPAE</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256161#M20413</link>
      <description>&lt;P&gt;In github repo "intel_fpga_bbb", there are several samples for us to refer. However, I do not find any examples containing IP. So, what should we do if we want to use IP in our project?&lt;/P&gt;
&lt;P&gt;From my perspective, what we should do is generate IP with Quartus Prime Pro and mv to "rtl/avalon" directory. But how should we modify sources.txt file, which records the source code of the project.&lt;/P&gt;</description>
      <pubDate>Mon, 15 Feb 2021 20:26:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256161#M20413</guid>
      <dc:creator>yiheng</dc:creator>
      <dc:date>2021-02-15T20:26:30Z</dc:date>
    </item>
    <item>
      <title>Re:how to use IP in OPAE</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256278#M20418</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;May I know which board are you targeting? &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;-Hazlina&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 16 Feb 2021 05:12:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256278#M20418</guid>
      <dc:creator>Hazlina_R_Intel</dc:creator>
      <dc:date>2021-02-16T05:12:06Z</dc:date>
    </item>
    <item>
      <title>Re: Re:how to use IP in OPAE</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256281#M20419</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P data-unlink="true"&gt;Thanks for your reply.I am working on vLab Academic Cluster and the board should be D5005 Programmable Acceleration Cards.&amp;nbsp; Its class name is fpga-pac-s10.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 16 Feb 2021 05:19:02 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/how-to-use-IP-in-OPAE/m-p/1256281#M20419</guid>
      <dc:creator>yiheng</dc:creator>
      <dc:date>2021-02-16T05:19:02Z</dc:date>
    </item>
  </channel>
</rss>

