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    <title>topic Allocating Memory Bandwidth in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1261543#M20486</link>
    <description>&lt;P&gt;I am getting familiar with memory bandwidth allocation and I wanted to make sure I am doing the right thing.&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;Commands:&lt;BR /&gt;sudo pqos -R&lt;BR /&gt;sudo pqos -e "mba@0:0=50;mba@0:1=50"&lt;BR /&gt;sudo pqos -a "llc:0=0-3;llc:1=4-9"&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Output:&amp;nbsp; sudo pqos -s&lt;/P&gt;
&lt;P&gt;NOTE: Mixed use of MSR and kernel interfaces to manage&lt;BR /&gt;CAT or CMT &amp;amp; MBM may lead to unexpected behavior.&lt;BR /&gt;L3CA/MBA COS definitions for Socket 0:&lt;BR /&gt;L3CA COS0 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS1 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS2 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS3 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS4 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS5 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS6 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS7 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS8 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS9 =&amp;gt; MASK 0x7ff&lt;BR /&gt;...&lt;BR /&gt;L3CA COS15 =&amp;gt; MASK 0x7ff&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;MBA COS0 =&amp;gt; 50% available&lt;BR /&gt;MBA COS1 =&amp;gt; 50% available&lt;BR /&gt;MBA COS2 =&amp;gt; 100% available&lt;BR /&gt;MBA COS3 =&amp;gt; 100% available&lt;BR /&gt;MBA COS4 =&amp;gt; 100% available&lt;BR /&gt;MBA COS5 =&amp;gt; 100% available&lt;BR /&gt;MBA COS6 =&amp;gt; 100% available&lt;BR /&gt;MBA COS7 =&amp;gt; 100% available&lt;BR /&gt;...&lt;BR /&gt;Core information for socket 0:&lt;BR /&gt;Core 0, L2ID 0, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 1, L2ID 1, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 2, L2ID 2, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 3, L2ID 3, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 4, L2ID 4, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 5, L2ID 8, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 6, L2ID 9, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 7, L2ID 10, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 8, L2ID 11, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 9, L2ID 12, L3ID 0 =&amp;gt; COS1, RMID0&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Confusion:&lt;/P&gt;
&lt;P&gt;AFAIK RMIDs are used to associate the specified configuration (as per this link: &lt;A href="https://01.org/cache-monitoring-technology" target="_blank"&gt;https://01.org/cache-monitoring-technology&lt;/A&gt;) but the RMID values for both the CLOS is same in my case. Is this alright, if not, how can I change that?&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 04 Mar 2021 20:55:57 GMT</pubDate>
    <dc:creator>amoghavs</dc:creator>
    <dc:date>2021-03-04T20:55:57Z</dc:date>
    <item>
      <title>Allocating Memory Bandwidth</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1261543#M20486</link>
      <description>&lt;P&gt;I am getting familiar with memory bandwidth allocation and I wanted to make sure I am doing the right thing.&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;Commands:&lt;BR /&gt;sudo pqos -R&lt;BR /&gt;sudo pqos -e "mba@0:0=50;mba@0:1=50"&lt;BR /&gt;sudo pqos -a "llc:0=0-3;llc:1=4-9"&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Output:&amp;nbsp; sudo pqos -s&lt;/P&gt;
&lt;P&gt;NOTE: Mixed use of MSR and kernel interfaces to manage&lt;BR /&gt;CAT or CMT &amp;amp; MBM may lead to unexpected behavior.&lt;BR /&gt;L3CA/MBA COS definitions for Socket 0:&lt;BR /&gt;L3CA COS0 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS1 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS2 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS3 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS4 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS5 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS6 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS7 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS8 =&amp;gt; MASK 0x7ff&lt;BR /&gt;L3CA COS9 =&amp;gt; MASK 0x7ff&lt;BR /&gt;...&lt;BR /&gt;L3CA COS15 =&amp;gt; MASK 0x7ff&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;MBA COS0 =&amp;gt; 50% available&lt;BR /&gt;MBA COS1 =&amp;gt; 50% available&lt;BR /&gt;MBA COS2 =&amp;gt; 100% available&lt;BR /&gt;MBA COS3 =&amp;gt; 100% available&lt;BR /&gt;MBA COS4 =&amp;gt; 100% available&lt;BR /&gt;MBA COS5 =&amp;gt; 100% available&lt;BR /&gt;MBA COS6 =&amp;gt; 100% available&lt;BR /&gt;MBA COS7 =&amp;gt; 100% available&lt;BR /&gt;...&lt;BR /&gt;Core information for socket 0:&lt;BR /&gt;Core 0, L2ID 0, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 1, L2ID 1, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 2, L2ID 2, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 3, L2ID 3, L3ID 0 =&amp;gt; COS0, RMID0&lt;BR /&gt;Core 4, L2ID 4, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 5, L2ID 8, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 6, L2ID 9, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 7, L2ID 10, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 8, L2ID 11, L3ID 0 =&amp;gt; COS1, RMID0&lt;BR /&gt;Core 9, L2ID 12, L3ID 0 =&amp;gt; COS1, RMID0&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Confusion:&lt;/P&gt;
&lt;P&gt;AFAIK RMIDs are used to associate the specified configuration (as per this link: &lt;A href="https://01.org/cache-monitoring-technology" target="_blank"&gt;https://01.org/cache-monitoring-technology&lt;/A&gt;) but the RMID values for both the CLOS is same in my case. Is this alright, if not, how can I change that?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 04 Mar 2021 20:55:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1261543#M20486</guid>
      <dc:creator>amoghavs</dc:creator>
      <dc:date>2021-03-04T20:55:57Z</dc:date>
    </item>
    <item>
      <title>Re:Allocating Memory Bandwidth</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1261627#M20491</link>
      <description>&lt;P&gt;Hello amoghavs,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Customer Support.&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;In order to better assist you, can you please provide us the model of the Intel(R) product that you need assistance with?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Sergio S.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;For firmware updates and troubleshooting tips, visit :&lt;A href="https://intel.com/support/serverbios" target="_blank"&gt;https://intel.com/support/serverbios&lt;/A&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 05 Mar 2021 02:47:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1261627#M20491</guid>
      <dc:creator>SergioS_Intel</dc:creator>
      <dc:date>2021-03-05T02:47:55Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Allocating Memory Bandwidth</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1262044#M20496</link>
      <description>&lt;P&gt;I found the clarification about this in the intel-cmt-cat wiki: &lt;A href="https://github.com/intel/intel-cmt-cat/wiki/MBM-MBA-how-to-guide" target="_blank"&gt;https://github.com/intel/intel-cmt-cat/wiki/MBM-MBA-how-to-guide&lt;/A&gt; , thank you.&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 06 Mar 2021 17:07:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1262044#M20496</guid>
      <dc:creator>amoghavs</dc:creator>
      <dc:date>2021-03-06T17:07:38Z</dc:date>
    </item>
    <item>
      <title>Re:Allocating Memory Bandwidth</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1262561#M20498</link>
      <description>&lt;P&gt;Hello amoghavs,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We are glad to hear you were able to resolve your problem. We are going to proceed and close this thread.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Sergio S.&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;For firmware updates and troubleshooting tips, visit :&lt;A href="https://intel.com/support/serverbios" rel="noopener noreferrer" target="_blank"&gt;https://intel.com/support/serverbios&lt;/A&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 09 Mar 2021 02:32:53 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1262561#M20498</guid>
      <dc:creator>SergioS_Intel</dc:creator>
      <dc:date>2021-03-09T02:32:53Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Allocating Memory Bandwidth</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1263236#M20520</link>
      <description>&lt;P&gt;This is an incomplete answer.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I had a couple of questions while I posted the question,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;1. Should allocation impact RMID or are the commands used "right"?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Answer: NO. RMID is related to monitoring, creating/altering COS should not impact RMID.&amp;nbsp;&lt;BR /&gt;More on RMIDs:&amp;nbsp;&lt;A href="https://software.intel.com/content/www/us/en/develop/blogs/intel-s-cache-monitoring-technology-software-visible-interfaces.html" target="_blank" rel="noopener"&gt;https://software.intel.com/content/www/us/en/develop/blogs/intel-s-cache-monitoring-technology-software-visible-interfaces.html&lt;/A&gt;&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;2. When does RMID actually change.&amp;nbsp;&lt;BR /&gt;Answer: RMIDs change when we are monitoring&lt;BR /&gt;Command:&amp;nbsp;&lt;/P&gt;
&lt;P&gt;cmd-1: sudo pqos -m "all:[0-3],[4-9]"&lt;/P&gt;
&lt;P&gt;cmd-2: sudo pqos -s&lt;/P&gt;
&lt;P&gt;While cmd-1 is running if we check on RMID status through cmd-2 in a different shell, this is the output we get:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Core information for socket 0:&lt;BR /&gt;Core 0, L2ID 0, L3ID 0 =&amp;gt; COS0, RMID1&lt;BR /&gt;Core 1, L2ID 1, L3ID 0 =&amp;gt; COS0, RMID1&lt;BR /&gt;Core 2, L2ID 2, L3ID 0 =&amp;gt; COS0, RMID1&lt;BR /&gt;Core 3, L2ID 3, L3ID 0 =&amp;gt; COS0, RMID1&lt;BR /&gt;Core 4, L2ID 4, L3ID 0 =&amp;gt; COS1, RMID2&lt;BR /&gt;Core 5, L2ID 8, L3ID 0 =&amp;gt; COS1, RMID2&lt;BR /&gt;Core 6, L2ID 9, L3ID 0 =&amp;gt; COS1, RMID2&lt;BR /&gt;Core 7, L2ID 10, L3ID 0 =&amp;gt; COS1, RMID2&lt;BR /&gt;Core 8, L2ID 11, L3ID 0 =&amp;gt; COS1, RMID2&lt;BR /&gt;Core 9, L2ID 12, L3ID 0 =&amp;gt; COS1, RMID2&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The output clearly shows that RMIDs are used based on groups of cores.&lt;/P&gt;</description>
      <pubDate>Wed, 10 Mar 2021 23:23:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Allocating-Memory-Bandwidth/m-p/1263236#M20520</guid>
      <dc:creator>amoghavs</dc:creator>
      <dc:date>2021-03-10T23:23:35Z</dc:date>
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