topic Re: Re:[EOIS] Xeon Phi 5110P configuring PCIe MEMBAR0 in Intel® Xeon® Processor and Server Products

Xeon Phi 5110P configuring PCIe MEMBAR0

CatalinP — Thu, 25 Mar 2021 01:25:01 GMT

Hello, I recently purchased an Intel Xeon Phi 5110P and reading through the Intel® Xeon Phi™ System Software Developer’s Guide (March, 2014).

In the section "2.1.12 Host and Intel® MIC Architecture Physical Memory Map" there is the following text:

MEMBAR0
 Relocatable in 64-bit System Physical Memory Address space
 Prefetchable
 32 GiB (max) down to 256 MiB (min)
 Programmable in Flash
 Offset into Intel® Xeon Phi™ coprocessor Physical Memory Address space
 Programmable in APR_PHY_BASE register
 Default is 0

How can I program the MEMBAR0 in Flash? I have searched in tools like micctrl, micflash and cannot find the option to configure the aperture. I would like to set the aperture to minimum size, 256 MB, to improve compatibility with other devices on the system.

Here is some additional information on my specific device:

Flash Version : 2.1.02.0391
Coprocessor Stepping : B1
Board SKU : B1PRQ-5110P/5120D

Thanks in advance!

Re:[EOIS] Xeon Phi 5110P configuring PCIe MEMBAR0

JoseH_Intel — Thu, 25 Mar 2021 02:50:58 GMT

Hello CatalinP,,

Thank you for joining the Intel community.

Due to this product being discontinued, Intel Customer Service no longer supports inquiries for it, but perhaps fellow community members have the knowledge to jump in and help. You may also find the Discontinued Products website helpful to address your request. Thank you for understanding.

The available software updates for this device are listed in the following URL: Intel® Manycore Platform Software Stack (Intel® MPSS)

Regards

Jose A.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit:

https://intel.com/support/serverbios

Re: Xeon Phi 5110P configuring PCIe MEMBAR0

phi__jack — Thu, 08 Apr 2021 12:59:48 GMT

Hi,

You need to enable the "Above 4G decoding" in bios.

Without it you can't use it.

Re: Re:[EOIS] Xeon Phi 5110P configuring PCIe MEMBAR0

CatalinP — Wed, 21 Apr 2021 04:56:07 GMT

Thanks JoseH and phi__jack for the replies.

I understand this product is no longer supported.. but I am thinking the phrase in SDG was there with good reason. Are there any internal documents regarding configuration of the bootloader? I have also heard that some additional documentation on Xeon Phi is available under NDA?

Thanks in advance.

Re: Re:[EOIS] Xeon Phi 5110P configuring PCIe MEMBAR0

phi__jack — Wed, 21 Apr 2021 21:27:24 GMT

Hi,
You want to understand how to do: you can download the mpss-4.4.1-card-source and you can learn from source code and have an idea.

Re: Re:[EOIS] Xeon Phi 5110P configuring PCIe MEMBAR0

CatalinP — Wed, 21 Apr 2021 23:46:05 GMT

Thank you, so far I have been studying mostly mpss-3.8.6 sources. Specifically I found code related to uploading a new flash image in src/mpss-micmgmt-3.8.6/apps/mpssflash/mpssflash.c. I have even used 'mpssflash read' to get the flash image to a local file, but no clues on how to configure MEMBAR0 size.

There is also some clues about boot process in host driver (src/mpss-modules-3.8.6/host/uos_download.c) and flash operations (src/mpss-modules-3.8.6/host/tools_support.c) but again nothing specific to MEMBAR0.

I have searched all mpss-3.8.6 sources for "MEMBAR0", nothing.

I have a copy of mpss-4.4.1-card-source but have not looked at it in detail yet. Seems a lot of modified versions of open-source packages (mpss-4.4.1/sources/card/sources/glibc-2.24.tar.xz). Is there much MIC-specific code there? If you have any tips where to look, please let me know.

Re: Re:[EOIS] Xeon Phi 5110P configuring PCIe MEMBAR0

phi__jack — Thu, 22 Apr 2021 09:09:26 GMT

Hi,
You can have more information from this link :https://community.intel.com/t5/Software-Archive/Accessing-Local-Resource-of-other-KCN/td-p/1050543