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    <title>topic Re:DDR5 Mode Register Read in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571426#M23749</link>
    <description>&lt;P&gt;Hello HRuck,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for your update.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We are waiting for your respond, please don't hesitate to ask any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Mon, 12 Feb 2024 07:38:54 GMT</pubDate>
    <dc:creator>IntelSupport</dc:creator>
    <dc:date>2024-02-12T07:38:54Z</dc:date>
    <item>
      <title>DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1569036#M23711</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am searching for a solution to do a DDR5 Mode Register Read on intel plattforms (Embedded processors preferred, but Server would also be a starting point). I have no idea about software, so i asked Chat GPT and it mentioned that this would be possible with IPP and Python. This lead me to this site and maybe somebody can give me some hint how to do this.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;So if you would have a "out of the box" solution, this would be nice, but I do not expect this and would be happy just if I could get a hint where to start.&lt;/P&gt;&lt;P&gt;Maybe some server vendors have a solution, maybe some open source is available to do this.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;So any hint and help is highly appreciated!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hermann&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 04 Feb 2024 18:04:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1569036#M23711</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-04T18:04:25Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570153#M23712</link>
      <description>&lt;P&gt;Hello HRuck,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for posting in Intel Communities. &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please allow us to check this internally with our team. You can be assured that we will keep you posted on any new development. &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Have a wonderful day!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards, &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;JCatulpos&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 07 Feb 2024 09:34:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570153#M23712</guid>
      <dc:creator>Catulpos_Intel</dc:creator>
      <dc:date>2024-02-07T09:34:45Z</dc:date>
    </item>
    <item>
      <title>Re: DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570202#M23713</link>
      <description>&lt;P&gt;Thanks a lot!!!&amp;nbsp;&lt;/P&gt;&lt;P&gt;looking forward to any feedback on this one!&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hermann&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 07 Feb 2024 12:54:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570202#M23713</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-07T12:54:39Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570440#M23714</link>
      <description>&lt;P&gt;Hello HRuck, &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;I hope you are doing well. &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;With regards to your concern, I would like to inform you that there is a specific forum for the query that you have and with that, kindly be informed that we will now move this to the server forum as you wanted to obtain further information regarding DDR5 mode register read on servers so your concern can be answered more quickly. &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for your kind understanding and have a nice day!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards, &lt;/P&gt;&lt;P&gt;JCatulpos&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&amp;nbsp;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 08 Feb 2024 02:57:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570440#M23714</guid>
      <dc:creator>Catulpos_Intel</dc:creator>
      <dc:date>2024-02-08T02:57:34Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570608#M23721</link>
      <description>&lt;P&gt;Hello Hermann,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: -apple-system, BlinkMacSystemFont, &amp;quot;Segoe UI&amp;quot;, system-ui, &amp;quot;Apple Color Emoji&amp;quot;, &amp;quot;Segoe UI Emoji&amp;quot;, &amp;quot;Segoe UI Web&amp;quot;, sans-serif; font-size: inherit;"&gt;Please allow us some time to review the details and we will get back with an update shortly.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: -apple-system, BlinkMacSystemFont, &amp;quot;Segoe UI&amp;quot;, system-ui, &amp;quot;Apple Color Emoji&amp;quot;, &amp;quot;Segoe UI Emoji&amp;quot;, &amp;quot;Segoe UI Web&amp;quot;, sans-serif; font-size: inherit;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: -apple-system, BlinkMacSystemFont, &amp;quot;Segoe UI&amp;quot;, system-ui, &amp;quot;Apple Color Emoji&amp;quot;, &amp;quot;Segoe UI Emoji&amp;quot;, &amp;quot;Segoe UI Web&amp;quot;, sans-serif; font-size: inherit;"&gt;Manoranjan Das&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 08 Feb 2024 14:16:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570608#M23721</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-08T14:16:01Z</dc:date>
    </item>
    <item>
      <title>Re: Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570677#M23723</link>
      <description>&lt;P&gt;Thanks a lot!&amp;nbsp;&lt;/P&gt;&lt;P&gt;for Servers I could add and clarify my needs:&lt;/P&gt;&lt;P&gt;e. g. trying to get the information out of the DRAM what the DRAM internal ECC mechanism documente (so not the Controller external ECC) is stored in the Mode Registers, so a MRR (Mode Register Read) is required.&lt;/P&gt;&lt;P&gt;Same if you want to get the training/configuration result out of the DRAM for Vref(CA/DQ) and DFE equalizer settings. Both are trained during power up and the result is stored in the Mode Register and can be retrieved with a MRR.&lt;/P&gt;&lt;P&gt;For Post package repair there are MRW (ModeRegister Write) and Mode Register Read needed.&lt;/P&gt;&lt;P&gt;All of these are functions that require to send Mode Register Write/Read and this is want I want to achieve..&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for any information.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hermann&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Feb 2024 18:12:10 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570677#M23723</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-08T18:12:10Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570930#M23728</link>
      <description>&lt;P&gt;Hello Hermann,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you reaching out intel community!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Since your request is related with a design for the embedded product. We request you to post your in Embedded Community link provided below.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.intel.com/t5/Embedded-Products/ct-p/embedded-products" target="_blank"&gt;https://community.intel.com/t5/Embedded-Products/ct-p/embedded-products&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;As we redirected you to the embedded community, we are closing this request.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please don't hesitate to ask any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 09 Feb 2024 09:28:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570930#M23728</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-09T09:28:30Z</dc:date>
    </item>
    <item>
      <title>Re: Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570937#M23729</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I do have the request for both Server (thats the reason why it was moved to this part) and Embedded.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I see much more chances to start with a server, so please do not close this, but leave it open to find a solution on server.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I wanted to do one step after the other, but after your comment i will ask the same question on the embedded side. Thanks for the link.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please check if you find any hint for server based Systems.&lt;/P&gt;&lt;P&gt;thanks a lot!&lt;/P&gt;&lt;P&gt;Hermann&lt;/P&gt;</description>
      <pubDate>Fri, 09 Feb 2024 09:40:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1570937#M23729</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-09T09:40:30Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571426#M23749</link>
      <description>&lt;P&gt;Hello HRuck,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for your update.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We are waiting for your respond, please don't hesitate to ask any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 12 Feb 2024 07:38:54 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571426#M23749</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-12T07:38:54Z</dc:date>
    </item>
    <item>
      <title>Re: DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571493#M23754</link>
      <description>&lt;P&gt;Not sure for for what resonse you are waiting ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;and especiually if this is not monitored .. how would you see any response?&lt;/P&gt;&lt;P&gt;looking forward to any answer&amp;nbsp; &amp;nbsp;&lt;LI-EMOJI id="lia_winking-face" title=":winking_face:"&gt;&lt;/LI-EMOJI&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hermann&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 12 Feb 2024 12:15:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571493#M23754</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-12T12:15:40Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571533#M23756</link>
      <description>&lt;P&gt;Hello HRuck,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you reaching out intel community!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Since issue related to DDR5 Mode Register Read validation with server and processor. You will receive a response from the embedded community.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please confirm if we can close this request as we redirected you to another community forum.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 12 Feb 2024 15:42:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571533#M23756</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-12T15:42:04Z</dc:date>
    </item>
    <item>
      <title>Re: DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571541#M23757</link>
      <description>&lt;P&gt;&amp;nbsp;am confused .. on top of this page there is mentioned this is a forum for server products.&amp;nbsp;&lt;/P&gt;&lt;P&gt;So it seems, that for any server related platform this is the correct forum.&lt;/P&gt;&lt;P&gt;So why redirecting this request to an embedded forum?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hermann&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 12 Feb 2024 16:08:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571541#M23757</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-12T16:08:24Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571830#M23759</link>
      <description>&lt;P&gt;Hello Hermann&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you reaching out intel community!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please allow us some time to review the details and we will get back with an update shortly.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 13 Feb 2024 08:44:10 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1571830#M23759</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-13T08:44:10Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1572196#M23769</link>
      <description>&lt;P&gt;Hello Hermann&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you reaching out intel community!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please allow us some time to review the details and we will get back with an update shortly.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Manoranjan Das.&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 14 Feb 2024 07:23:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1572196#M23769</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-14T07:23:51Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1572542#M23775</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 12px;"&gt;Hello HRuck,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12px;"&gt;Thank you reaching out intel community!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12px; font-family: sans-serif;"&gt;Since your query related to design, we are redirecting to the embedded community forum.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12px;"&gt;Please confirm if we can close this request as we redirected you to another community forum.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12px;"&gt;Regards&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12px;"&gt;Manoranjan Das&lt;/SPAN&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 15 Feb 2024 07:38:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1572542#M23775</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-15T07:38:04Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1573818#M23796</link>
      <description>&lt;P&gt;Hello HRuck,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings for the day!&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We would like to inform you that we are closing this request as no response has been received from our previous follow-ups.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please don't hesitate to ask any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 20 Feb 2024 10:10:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1573818#M23796</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-20T10:10:21Z</dc:date>
    </item>
    <item>
      <title>Re: Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1573828#M23797</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am confused again .. beside a&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Please allow us some time to review the details and we will get back with an update shortly.&lt;/P&gt;&lt;P&gt;There was not response from your side ..&amp;nbsp;&lt;/P&gt;&lt;P&gt;Guess i need to open a new thread with the same topic if this will not be longer monitored..&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hemrann&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 20 Feb 2024 11:22:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1573828#M23797</guid>
      <dc:creator>HRuck</dc:creator>
      <dc:date>2024-02-20T11:22:46Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1574201#M23806</link>
      <description>&lt;P&gt;Hello HRuck,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings for the day!&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your update, we will wait for your response.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please don't hesitate to ask any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Manoranjan Das&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 21 Feb 2024 13:00:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1574201#M23806</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-21T13:00:22Z</dc:date>
    </item>
    <item>
      <title>Re:DDR5 Mode Register Read</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1575324#M23826</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;Hello HRuck&lt;/SPAN&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;Greetings for the day!&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;We would like to inform you that we are closing this request as no response has been received from our previous follow-ups.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;Please don't hesitate to ask any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: inherit;"&gt;Manoranjan Das&lt;/SPAN&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 26 Feb 2024 07:41:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/DDR5-Mode-Register-Read/m-p/1575324#M23826</guid>
      <dc:creator>IntelSupport</dc:creator>
      <dc:date>2024-02-26T07:41:47Z</dc:date>
    </item>
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