topic Re:Intel MRC training document In coreboot in Intel® Xeon® Processor and Server Products

Intel MRC training document In coreboot

nl_jk — Thu, 18 Dec 2025 23:20:32 GMT

Hello,

I built coreboot (x32) + EDK2 (x32) and coreboot (x32) + EDK2 (x64) successfully. These combinations have some side effects on memory management.
So, I tried coreboot (x64) + EDK2 (x64) but failed around Intel MRC binary.
can you provide some information to build this combination? And how can I get Intel MRC-related document?

Thanks,

Re: Intel MRC training document In coreboot

nl_jk — Thu, 18 Dec 2025 23:27:38 GMT

I am using Intel Archer City reference platform..

Re:Intel MRC training document In coreboot

Amina_Sadiya — Fri, 19 Dec 2025 10:29:37 GMT

Hello nl_jk,

Greetings from Intel!

Thank you for contacting Intel. To proceed further with your query, I kindly request that you share the below details:

1. Product details

2. System details

3. Elaborate the issue that you are facing.

Please feel free to respond to this email at your earliest convenience.

Regards,

Amina

Intel Customer Support Technician

Re:Intel MRC training document In coreboot

Amina_Sadiya — Mon, 22 Dec 2025 11:11:13 GMT

Hello Team,

Greetings from Intel.

This is the follow-up regarding the reported issue. We're eager to ensure a swift resolution and would appreciate any updates or additional information you can provide.

If we don't hear back from you, we'll assume the issue has been resolved and will proceed to close the case.

Please feel free to respond to this email at your earliest convenience.

Regards,

Amina

Intel Customer Support Technician

Re: Re:Intel MRC training document In coreboot

nl_jk — Thu, 22 Jan 2026 23:57:05 GMT

Hi,

Product code: S2EG2SE36Q (Engineering sample)

Serial No. : CSA224800014

platform: Eagle Stream

Processor: Sapphire Rapids ES2/QS

Board Name: Archer City RP

Phase: Qual

My goal: reading DDR5 SPD and configuring MRC

My test configuration is Coreboot + EDK2,

Intel FSP is extracted from default BIOS (EGSDCRB1.SYS.WR.64.2022.51.1.02.1552.1_9409.P01_SPR_EBG_SPS_IPClean_Production_Pfr_Container_BtgP0)

1. coreboot (X64) + edk2 (x64): build failure.. (around FSP code)

2. how to get DDR5 SPD via Intel FSP, any document..

Thanks,

Junkil Ryu