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    <title>topic Re:Question about CXL read bandwidth monitoring on 4th Gen Intel Xeon (Sapphire Rapids) with PCM in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747090#M27333</link>
    <description>&lt;P&gt;Hi countingStars,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings for the day!&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Support. We acknowledge receipt of your concern and would like to assure you that assisting you is our top priority.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We kindly request you to share the complete product details and system information. Providing this information will help us diagnose and resolve the issue more efficiently.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We look forward to your response.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Poojitha N&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Thu, 07 May 2026 10:59:35 GMT</pubDate>
    <dc:creator>Poojitha</dc:creator>
    <dc:date>2026-05-07T10:59:35Z</dc:date>
    <item>
      <title>Question about CXL read bandwidth monitoring on 4th Gen Intel Xeon (Sapphire Rapids) with PCM</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747031#M27332</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P class=""&gt;&lt;SPAN&gt;Hi all,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;I’ve been experimenting with Intel’s PCM tool to monitor CXL memory traffic on a 4th Gen Xeon (Sapphire Rapids) system.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;Here’s what I observed:&lt;/SPAN&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P class=""&gt;&lt;STRONG&gt;&lt;SPAN&gt;Write bandwidth&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;to a CXL memory device can be reliably measured using&lt;/SPAN&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA.&lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;This works as expected and gives device statistics.&lt;/SPAN&gt;&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P class=""&gt;&lt;STRONG&gt;&lt;SPAN&gt;Read bandwidth&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;from the same CXL device, however, cannot be measured using the corresponding Rx event&lt;/SPAN&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA&lt;/STRONG&gt;&lt;/EM&gt;&lt;SPAN&gt;&amp;nbsp;– it always shows zero, even under heavy read traffic.&lt;/SPAN&gt;&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P class=""&gt;&lt;SPAN&gt;Instead, on Sapphire Rapids (where&amp;nbsp;&lt;/SPAN&gt;nearMemoryMetricsAvailable()&lt;SPAN&gt;&amp;nbsp;returns&amp;nbsp;&lt;/SPAN&gt;false&lt;SPAN&gt;), PCM falls back to CHA‑based events like&lt;/SPAN&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC&lt;/EM&gt;&lt;/STRONG&gt;&lt;SPAN&gt;, which only provide&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;&lt;SPAN&gt;socket‑level&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;read bandwidth for CXL device.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;From the Intel PCM source code (pcm-memory.cpp, cpucounters.h), I understand that on newer platforms like Granite Rapids or Sierra Forest (&lt;/SPAN&gt;nearMemoryMetricsAvailable() == true&lt;SPAN&gt;), the UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA&amp;nbsp;event&amp;nbsp;&lt;/SPAN&gt;&lt;EM&gt;&lt;SPAN&gt;does&lt;/SPAN&gt;&lt;/EM&gt;&lt;SPAN&gt;&amp;nbsp;work and gives per‑CXL‑device read bandwidth. So the difference is clearly platform‑dependent.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;My main question is:&amp;nbsp;On 4th Generation Intel Xeon (Sapphire Rapids), &lt;STRONG&gt;why is it impossible to obtain CXL read bandwidth via the event&amp;nbsp;&lt;EM&gt;UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA&lt;/EM&gt;&lt;/STRONG&gt;?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;What is the architectural or microarchitectural reason that prevents&amp;nbsp;&lt;/SPAN&gt;UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA&lt;SPAN&gt;&amp;nbsp;from counting reads on these “traditional” platforms?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;Thank you in advance for any insights!&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;Countingstars&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 07 May 2026 01:30:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747031#M27332</guid>
      <dc:creator>countingStars</dc:creator>
      <dc:date>2026-05-07T01:30:07Z</dc:date>
    </item>
    <item>
      <title>Re:Question about CXL read bandwidth monitoring on 4th Gen Intel Xeon (Sapphire Rapids) with PCM</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747090#M27333</link>
      <description>&lt;P&gt;Hi countingStars,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings for the day!&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Support. We acknowledge receipt of your concern and would like to assure you that assisting you is our top priority.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We kindly request you to share the complete product details and system information. Providing this information will help us diagnose and resolve the issue more efficiently.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We look forward to your response.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Poojitha N&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 07 May 2026 10:59:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747090#M27333</guid>
      <dc:creator>Poojitha</dc:creator>
      <dc:date>2026-05-07T10:59:35Z</dc:date>
    </item>
    <item>
      <title>Re:Question about CXL read bandwidth monitoring on 4th Gen Intel Xeon (Sapphire Rapids) with PCM</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747780#M27350</link>
      <description>&lt;P&gt;Hi countingStars,&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Greetings for the day!&amp;nbsp;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;We are following up to check if you were able to find the information we requested. Kindly confirm at your earliest convenience, so that we can continue assisting you in resolving this matter.&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;We appreciate your understanding!&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Regards,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Poojitha&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 13 May 2026 10:58:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Question-about-CXL-read-bandwidth-monitoring-on-4th-Gen-Intel/m-p/1747780#M27350</guid>
      <dc:creator>Poojitha</dc:creator>
      <dc:date>2026-05-13T10:58:36Z</dc:date>
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