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    <title>Thema "Stitched Rank Margin Test Log Format" in Intel® Xeon® Processor and Server Products</title>
    <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1749933#M27385</link>
    <description>&lt;DIV&gt;&lt;SPAN&gt;Hi could someone help me to figure out the format for the RMT logs?&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;I am currently using the Rank Margin Test to validate some DIMMs for an Intel Xeon Silver 4310 CPU (Ice Lake). I am able to run the Stitched Rank Margin Test, but I am having issues with the log output. I am using the Memory Assistant for Intel Xeon Platforms 2.8.26.0 application to analyze the RMT serial log output and the main tab in the application runs fine, but the UPM tab is not letting me click on "Run UPM" due to lack of DIMM information. Could you provide an example of what information the log is supposed to include so that UPM will run properly?&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Output of RMT test:&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_1-1780432603947.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72860iCD02F33BD78A2BE9/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_1-1780432603947.png" alt="tester_1_1-1780432603947.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Log that I compiled from serial output of RMT test:&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_0-1780432432206.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72857i510E69897E7FC3D3/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_0-1780432432206.png" alt="tester_1_0-1780432432206.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Memory Assistant for Intel Xeon Platforms 2.8.26.0 Main Tab:&lt;/SPAN&gt;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_0-1780432554332.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72859i19F7797CDDEEC012/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_0-1780432554332.png" alt="tester_1_0-1780432554332.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Memory Assistant for Intel Xeon Platforms 2.8.26.0 UPM Tab:&lt;/SPAN&gt;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_1-1780432461126.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72858i346115ACD7A2DFA8/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_1-1780432461126.png" alt="tester_1_1-1780432461126.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;</description>
    <pubDate>Tue, 02 Jun 2026 20:37:06 GMT</pubDate>
    <dc:creator>tester_1</dc:creator>
    <dc:date>2026-06-02T20:37:06Z</dc:date>
    <item>
      <title>Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1749933#M27385</link>
      <description>&lt;DIV&gt;&lt;SPAN&gt;Hi could someone help me to figure out the format for the RMT logs?&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;I am currently using the Rank Margin Test to validate some DIMMs for an Intel Xeon Silver 4310 CPU (Ice Lake). I am able to run the Stitched Rank Margin Test, but I am having issues with the log output. I am using the Memory Assistant for Intel Xeon Platforms 2.8.26.0 application to analyze the RMT serial log output and the main tab in the application runs fine, but the UPM tab is not letting me click on "Run UPM" due to lack of DIMM information. Could you provide an example of what information the log is supposed to include so that UPM will run properly?&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Output of RMT test:&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_1-1780432603947.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72860iCD02F33BD78A2BE9/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_1-1780432603947.png" alt="tester_1_1-1780432603947.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Log that I compiled from serial output of RMT test:&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_0-1780432432206.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72857i510E69897E7FC3D3/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_0-1780432432206.png" alt="tester_1_0-1780432432206.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Memory Assistant for Intel Xeon Platforms 2.8.26.0 Main Tab:&lt;/SPAN&gt;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_0-1780432554332.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72859i19F7797CDDEEC012/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_0-1780432554332.png" alt="tester_1_0-1780432554332.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Memory Assistant for Intel Xeon Platforms 2.8.26.0 UPM Tab:&lt;/SPAN&gt;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_1-1780432461126.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72858i346115ACD7A2DFA8/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_1-1780432461126.png" alt="tester_1_1-1780432461126.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 02 Jun 2026 20:37:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1749933#M27385</guid>
      <dc:creator>tester_1</dc:creator>
      <dc:date>2026-06-02T20:37:06Z</dc:date>
    </item>
    <item>
      <title>Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1749969#M27386</link>
      <description>&lt;P&gt;Hi tester_1,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings for the day!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for contacting Intel Customer Support with your query:&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please refer the below document for Memory Assistant for Intel® Xeon® Platforms.&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/secure/content-details/620497/memory-assistant-for-intel-xeon-platforms.html?DocID=620497" rel="noopener noreferrer" target="_blank"&gt;Memory Assistant for Intel® Xeon® Platforms&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Note: This document requires Intel RDC access.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;For RDC access, you can refer to the below article.&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html" rel="noopener noreferrer" target="_blank"&gt;How to Apply for an Intel® Resource and Documentation Center (RDC)...&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Jerome&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 03 Jun 2026 05:37:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1749969#M27386</guid>
      <dc:creator>Steve_Jerome22</dc:creator>
      <dc:date>2026-06-03T05:37:04Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750037#M27388</link>
      <description>&lt;P&gt;Hi Jerome,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for providing me the documents, but it does not contain an example of what the log file should look like/include. I also looked at the Whitley Platform DDR4 EV Tools and Methodology (ID: 611498) document and it does not show what the full log should include. I think I am missing some DIMM information that is preventing me from running the UPM assessment, so would it be possible for you to provide a full example of a stitched RMT log?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;</description>
      <pubDate>Wed, 03 Jun 2026 16:31:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750037#M27388</guid>
      <dc:creator>tester_1</dc:creator>
      <dc:date>2026-06-03T16:31:15Z</dc:date>
    </item>
    <item>
      <title>Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750046#M27389</link>
      <description>&lt;P&gt;Hello tester_1,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Kindly provide the environment details, including the server model and operating system, so that we can review this internally  and assist you accordingly.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yesu27_Intel&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 03 Jun 2026 19:04:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750046#M27389</guid>
      <dc:creator>Yesu27</dc:creator>
      <dc:date>2026-06-03T19:04:36Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750072#M27390</link>
      <description>&lt;P&gt;Hi Yesu_27,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for taking a look at the issue. I am currently running WilsonCity System BIOS Version: K13P1N12 Date: "09/30/2022" with Ubuntu 22.04.5 LTS. I am running this on an Everpure Flashblade S200. I just wanted to note that the output the RMT test is the serial output when the system is booting up. Also, I was reading the Whitley/Cedar Island DDR EV overview and tool update document (ID: 621731) and saw that there was a DIMMINFO table in the serial log. Do you know how to adjust the BIOS or any settings for the DIMMINFO table to show up and how would I include it in the RMT log?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;DIMMINFO Table:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="tester_1_0-1780529734310.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/72877i1BFCDB4166358998/image-size/medium?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="tester_1_0-1780529734310.png" alt="tester_1_0-1780529734310.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 03 Jun 2026 23:36:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750072#M27390</guid>
      <dc:creator>tester_1</dc:creator>
      <dc:date>2026-06-03T23:36:47Z</dc:date>
    </item>
    <item>
      <title>Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750080#M27391</link>
      <description>&lt;P&gt;Hello tester_1,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings for the day!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for sharing the requested information, please allow us some time to check and provide you with an update as soon as possible.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for your understanding.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Jerome&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 04 Jun 2026 01:31:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750080#M27391</guid>
      <dc:creator>Steve_Jerome22</dc:creator>
      <dc:date>2026-06-04T01:31:21Z</dc:date>
    </item>
    <item>
      <title>Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750096#M27393</link>
      <description>&lt;P&gt;Hello tester_1,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Since the query is out of our scope, we will be transferring the case to the concern team.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;You will be assisted further on this case by Intel SDP team.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for your understanding.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Jerome&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 04 Jun 2026 04:17:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750096#M27393</guid>
      <dc:creator>Steve_Jerome22</dc:creator>
      <dc:date>2026-06-04T04:17:41Z</dc:date>
    </item>
    <item>
      <title>Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750100#M27394</link>
      <description>&lt;P&gt;Hello tester_1,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Apologies, kindly ignore the previous post.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We request to open a new ticket in the Intel Software Development Platform Support Center (Intel SDP) using the following link &lt;A href="http://www.intel.com/sdp" target="_blank"&gt;http://www.intel.com/sdp&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Or if you have access to Intel Premier Support, you can open an IPS support ticket &lt;/P&gt;&lt;P&gt;&lt;A href="https://premiersupport.intel.com/" target="_blank"&gt;https://premiersupport.intel.com/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for your understanding.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Jerome&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 04 Jun 2026 05:21:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750100#M27394</guid>
      <dc:creator>Steve_Jerome22</dc:creator>
      <dc:date>2026-06-04T05:21:09Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750168#M27401</link>
      <description>&lt;P&gt;Hi Jerome,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for letting me know. I have created an IPS support ticket.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best,&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;</description>
      <pubDate>Thu, 04 Jun 2026 16:21:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750168#M27401</guid>
      <dc:creator>tester_1</dc:creator>
      <dc:date>2026-06-04T16:21:16Z</dc:date>
    </item>
    <item>
      <title>Re:Stitched Rank Margin Test Log Format</title>
      <link>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750171#M27402</link>
      <description>&lt;P&gt;Hi tester_1,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Greetings!&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for your response. Since you have created IPS ticket, we are closing this request. Please don’t hesitate to reach out with any further questions in the future. Feel free to start a new conversation, as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Dinesh&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 04 Jun 2026 17:52:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Xeon-Processor-and-Server/Stitched-Rank-Margin-Test-Log-Format/m-p/1750171#M27402</guid>
      <dc:creator>Dineshbabu</dc:creator>
      <dc:date>2026-06-04T17:52:08Z</dc:date>
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