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    <title>topic Re: Questions about memory cache control in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920478#M13303</link>
    <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;We are forwarding your question to our engineering contacts and will let you know how they respond.&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Adetailed discussion of memory cache control can also be found in Chapter 10 of the IA-32 Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide (&lt;A href="http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol3" target="_blank"&gt;http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol3&lt;/A&gt;).&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;12-02-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;08:41 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 27 Jan 2005 06:21:37 GMT</pubDate>
    <dc:creator>Intel_Software_Netw1</dc:creator>
    <dc:date>2005-01-27T06:21:37Z</dc:date>
    <item>
      <title>Questions about memory cache control</title>
      <link>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920477#M13302</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;First of all, thanks for your reading.&lt;/DIV&gt;
&lt;DIV&gt;I havetwo questions about memory cache control.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt; "1. Do store buffers operate when disabling caches?"&lt;/DIV&gt;
&lt;DIV&gt; "2.Ifsome memory regions are set to WC(write combining), dothe readsto the regionsrefer to write combining buffers, not to memory? If the reads refer to write combining buffers, is it possible toflush the buffer explicitly?"&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;If you have any idea, please let me know.&lt;/DIV&gt;
&lt;DIV&gt;I look forward to replying.&lt;/DIV&gt;
&lt;P&gt;Message Edited by changhee on &lt;SPAN class="date_text"&gt;01-07-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;10:12 AM&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Message Edited by changhee on &lt;SPAN class="date_text"&gt;01-07-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;10:16 AM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 08 Jan 2005 02:06:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920477#M13302</guid>
      <dc:creator>changhee</dc:creator>
      <dc:date>2005-01-08T02:06:50Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about memory cache control</title>
      <link>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920478#M13303</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;We are forwarding your question to our engineering contacts and will let you know how they respond.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Adetailed discussion of memory cache control can also be found in Chapter 10 of the IA-32 Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide (&lt;A href="http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol3" target="_blank"&gt;http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol3&lt;/A&gt;).&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;12-02-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;08:41 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 27 Jan 2005 06:21:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920478#M13303</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2005-01-27T06:21:37Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about memory cache control</title>
      <link>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920479#M13304</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Here is the response we received from our engineering contacts:&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;NAMESPACE prefix="o" ns="urn:schemas-microsoft-com:office:office"&gt;&lt;P&gt;&lt;/P&gt;&lt;/NAMESPACE&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;BLOCKQUOTE dir="ltr" style="MARGIN-RIGHT: 0px"&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;Q1. Do store buffers operate when disabling caches?&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;A1. Yes. Store buffers operate regardless of the memory type of the target address or whether cache is disabled or not. &lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;Q2. If some memory regions are set to WC (write combining), do the reads to the regions refer to write combining buffers, not to memory? If the reads refer to write combining buffers, is it possible to flush the buffer explicitly?&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;FONT face="Arial" color="green" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;P&gt;A2. Yes. If the write combine buffer is not flushed, the data will come from the WC buffer. Cache Line Flush instruction (clflush) will flush the cache line containing the specified address from all levels.&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;
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&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;12-02-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;08:41 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Feb 2005 05:23:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Questions-about-memory-cache-control/m-p/920479#M13304</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2005-02-08T05:23:05Z</dc:date>
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