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    <title>topic Re: #SS in #SS in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926172#M13892</link>
    <description>&lt;DIV&gt;&lt;/DIV&gt;
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&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Our engineers would like to know which CPU(s) you are specifically asking about. Thanks in advance for your clarification.&lt;/FONT&gt;&lt;/DIV&gt;
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    <pubDate>Wed, 01 Dec 2004 05:57:34 GMT</pubDate>
    <dc:creator>Intel_Software_Netw1</dc:creator>
    <dc:date>2004-12-01T05:57:34Z</dc:date>
    <item>
      <title>#SS in #SS</title>
      <link>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926171#M13891</link>
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&lt;DIV&gt;I want to know how CPU behave when there's no stack available(SS:ESP points to an virtual address which is not mapped to physical memory). The environment is in protection-mode. Following is my understanding:&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Because there's no PTE for stack, the instruction "push eax" will result in a #SS. Responding to this #SS, the CPU will push EFLAGS, CS, EIP and ERROR_CODE into stack and turn to exception handler. But the new push will generate new #SS for the same reason... and the process will deadlock here. &lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Is my understanding correct?&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thanks,&lt;/DIV&gt;
&lt;DIV&gt;Min&lt;/DIV&gt;&lt;/DIV&gt;
&lt;P&gt;Message Edited by minwang on &lt;SPAN class="date_text"&gt;11-23-2004&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;06:23 PM&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Message Edited by minwang on &lt;SPAN class="date_text"&gt;11-23-2004&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;06:24 PM&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Message Edited by minwang on &lt;SPAN class="date_text"&gt;11-23-2004&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;06:31 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Message Edited by minwang on &lt;SPAN class="date_text"&gt;11-24-2004&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;03:02 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 23 Nov 2004 09:31:31 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926171#M13891</guid>
      <dc:creator>minwang</dc:creator>
      <dc:date>2004-11-23T09:31:31Z</dc:date>
    </item>
    <item>
      <title>Re: #SS in #SS</title>
      <link>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926172#M13892</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Our engineers would like to know which CPU(s) you are specifically asking about. Thanks in advance for your clarification.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;P class="MsoNormal" style="MARGIN: 0in 0in 0pt"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: black; FONT-FAMILY: Arial"&gt;&lt;A href="http://www.intel.com/cd/ids/developer/asmo-na/eng/58987.htm" target="_blank"&gt;Contact us&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/FONT&gt;&lt;P&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;12-02-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;01:11 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 01 Dec 2004 05:57:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926172#M13892</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2004-12-01T05:57:34Z</dc:date>
    </item>
    <item>
      <title>Re: #SS in #SS</title>
      <link>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926173#M13893</link>
      <description>I would not think a deadlock would occur becuase the I think the CPU is already acknowledged it's generating an exception, if an exception occurs whilst in one a double fault occurs resulting in a CPU reset. Not sure if all models do that.&lt;BR /&gt;</description>
      <pubDate>Sat, 15 Aug 2009 17:15:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/SS-in-SS/m-p/926173#M13893</guid>
      <dc:creator>chazzeromus</dc:creator>
      <dc:date>2009-08-15T17:15:00Z</dc:date>
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