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    <title>topic Hi divakar, in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930138#M14604</link>
    <description>&lt;P&gt;Hi divakar,&lt;/P&gt;

&lt;P&gt;Signal can be used for transfering data asynchronously from the device to the host as well. Please refer to "About Asynchronous Data Trannsfer" (&lt;A href="http://software.intel.com/en-us/node/459120"&gt;http://software.intel.com/en-us/node/459120&lt;/A&gt;). In this section, code sample demonstrates&amp;nbsp;how to transfer data&amp;nbsp;to and from the coprocessor asynchronously. Thank you.&lt;/P&gt;</description>
    <pubDate>Wed, 11 Dec 2013 19:28:13 GMT</pubDate>
    <dc:creator>Loc_N_Intel</dc:creator>
    <dc:date>2013-12-11T19:28:13Z</dc:date>
    <item>
      <title>Pipelining offloads</title>
      <link>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930135#M14601</link>
      <description>&lt;P&gt;I have a basic question. Suppose I offload the following three items ASYNCHRONOUSLY to the same mic device from the same thread on the host.&lt;/P&gt;

&lt;P&gt;1. Offload a bunch of data tied to a pointer v at the host (in clause)&lt;/P&gt;

&lt;P&gt;2. Offload a function call one of whose arguments is the pointer v&lt;/P&gt;

&lt;P&gt;3. Offload a data output from the mic device to the pointer v (out clause)&lt;/P&gt;

&lt;P&gt;Is it correct to assume that the mic device does not start running the function in&amp;nbsp;#2 until the data input to it in #1 is complete? Is it correct to assume that the mic device does not do the data output in #3 until the function call in #2 is complete?&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 05 Dec 2013 22:47:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930135#M14601</guid>
      <dc:creator>Anonymous</dc:creator>
      <dc:date>2013-12-05T22:47:44Z</dc:date>
    </item>
    <item>
      <title>When you offload</title>
      <link>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930136#M14602</link>
      <description>&lt;P&gt;When you offload asynchronously you should not depend on previous offload completing before the current.&amp;nbsp; You need to use signal/wait to control the order.&lt;/P&gt;</description>
      <pubDate>Fri, 06 Dec 2013 00:56:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930136#M14602</guid>
      <dc:creator>Ravi_N_Intel</dc:creator>
      <dc:date>2013-12-06T00:56:05Z</dc:date>
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    <item>
      <title>Thank you --- that is what I</title>
      <link>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930137#M14603</link>
      <description>&lt;P&gt;Thank you --- that is what I expected.&lt;/P&gt;

&lt;P&gt;The Intel compiler manual says the following about signal (under #pragma offload signal as well as #pragma offload_transfer signal):&lt;/P&gt;

&lt;DL&gt;
	&lt;DT class="dlterm" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em; width: 100px; color: rgb(51, 51, 51); font-family: Helvetica, sans-serif; font-size: 15px; font-weight: normal; line-height: normal;"&gt;&lt;SAMP class="codeph" style="font-family: 'Courier New', Courier, monospace;"&gt;&lt;VAR&gt;signal&lt;/VAR&gt;&lt;/SAMP&gt;&lt;/DT&gt;
	&lt;DD style="font-size: 15px; margin-left: 0px; position: relative; top: -13pt; left: 110px; width: 556.5px; line-height: 14pt; margin-top: 0em; margin-bottom: -10pt; color: rgb(51, 51, 51); font-family: Helvetica, sans-serif;"&gt;
		&lt;P style="font-size: inherit; line-height: 22px; margin-top: 0em; margin-bottom: 0em;"&gt;An optional integer expression that serves as a handle on an asynchronous data transfer or computational activity. The computation performed by the&lt;SAMP class="codeph" style="font-family: 'Courier New', Courier, monospace;"&gt;offload&lt;/SAMP&gt;&amp;nbsp;clause and any results returned from the offload using&amp;nbsp;&lt;SAMP class="codeph" style="font-family: 'Courier New', Courier, monospace;"&gt;out&lt;/SAMP&gt;&amp;nbsp;clauses occurs concurrently with CPU execution of the code after the pragma. If this clause is not used, then the entire offload and associated data transfer are executed synchronously. The CPU will not continue past the pragma until it has completed.&lt;/P&gt;

		&lt;P style="font-size: inherit; line-height: 22px; margin-top: 0em; margin-bottom: 0em;"&gt;This clause refers to a specific target device so you must specify a&amp;nbsp;&lt;VAR&gt;target-number&amp;nbsp;&lt;/VAR&gt;in the&amp;nbsp;&lt;SAMP class="codeph" style="font-family: 'Courier New', Courier, monospace;"&gt;target&lt;/SAMP&gt;&amp;nbsp;clause that is greater than or equal to zero.&lt;/P&gt;

		&lt;P style="font-size: inherit; line-height: 22px; margin-top: 0em; margin-bottom: 0em;"&gt;&amp;nbsp;&lt;/P&gt;
	&lt;/DD&gt;
&lt;/DL&gt;

&lt;P&gt;Why does the documentation not refer to the in clauses as opposed to out? Can we assume that in clauses inputting data from host to device also occur concurrently?&lt;/P&gt;

&lt;P&gt;I assume that the async&amp;nbsp;transfers are&amp;nbsp;done using DMA. If so, memory on the host needs to be pinned or registered to prevent memory from being paged out. At what point is the memory pinned and then unpinned?&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 06 Dec 2013 20:24:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930137#M14603</guid>
      <dc:creator>Anonymous</dc:creator>
      <dc:date>2013-12-06T20:24:52Z</dc:date>
    </item>
    <item>
      <title>Hi divakar,</title>
      <link>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930138#M14604</link>
      <description>&lt;P&gt;Hi divakar,&lt;/P&gt;

&lt;P&gt;Signal can be used for transfering data asynchronously from the device to the host as well. Please refer to "About Asynchronous Data Trannsfer" (&lt;A href="http://software.intel.com/en-us/node/459120"&gt;http://software.intel.com/en-us/node/459120&lt;/A&gt;). In this section, code sample demonstrates&amp;nbsp;how to transfer data&amp;nbsp;to and from the coprocessor asynchronously. Thank you.&lt;/P&gt;</description>
      <pubDate>Wed, 11 Dec 2013 19:28:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Pipelining-offloads/m-p/930138#M14604</guid>
      <dc:creator>Loc_N_Intel</dc:creator>
      <dc:date>2013-12-11T19:28:13Z</dc:date>
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