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    <title>topic Re: IA32_CTL Model Specific Register in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939480#M16699</link>
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&lt;DIV&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;12-01-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;07:11 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 26 Jan 2005 01:54:49 GMT</pubDate>
    <dc:creator>Intel_Software_Netw1</dc:creator>
    <dc:date>2005-01-26T01:54:49Z</dc:date>
    <item>
      <title>IA32_CTL Model Specific Register</title>
      <link>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939479#M16698</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Hello,&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;My question is regarding the Model Specific Registers (MSRs) of the Pentium 4 family. I have been refering to the following application note -&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="6"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="6"&gt;&lt;FONT size="2"&gt;IA-32 Intel&lt;/FONT&gt;&lt;/FONT&gt;&lt;FONT size="2"&gt; &lt;/FONT&gt;&lt;FONT size="2"&gt;Architecture, &lt;/FONT&gt;&lt;FONT size="2"&gt;Software Developers &lt;/FONT&gt;&lt;FONT size="2"&gt;Manual, &lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Volume 3: &lt;/FONT&gt;&lt;FONT size="2"&gt;System Programming Guide&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;The MSR "IA32_CTL" located at address 0x17B (379)isdescribed asthe "Machine Check Feature Enable". &lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;However, the manual never states the Processor Model (0,1,2 or 3) for which this MSR is available.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Moreover for a HyperThreaded Machine, the manual does not specify whether this MSR is shared / unique among the available logical processors.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Can some one clarify my doubts ?&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Mithun Shanbhag&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Syracuse University.&lt;/FONT&gt;&lt;/DIV&gt;
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      <pubDate>Mon, 13 Sep 2004 10:23:48 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939479#M16698</guid>
      <dc:creator>mrshanbh</dc:creator>
      <dc:date>2004-09-13T10:23:48Z</dc:date>
    </item>
    <item>
      <title>Re: IA32_CTL Model Specific Register</title>
      <link>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939480#M16699</link>
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&lt;DIV&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;12-01-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;07:11 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jan 2005 01:54:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939480#M16699</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2005-01-26T01:54:49Z</dc:date>
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    <item>
      <title>Re: IA32_CTL Model Specific Register</title>
      <link>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939481#M16700</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;FONT color="#330000"&gt;Our engineers responded as follows:&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
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&lt;DIV align="left"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;Although this MSR is architecturally defined in the System Programming Guide (Vol 3 of the &lt;A href="http://developer.intel.com/design/Pentium4/documentation.htm" target="_blank"&gt;IA-32 Intel Architecture, Software Developers Manual&lt;/A&gt;), the specific entry in Chapter 13 (on MCA), does not guarantee that this MSR will be implemented in any specific processor. You should test for the presence of this feature by checking the capability flag MCG_CTL_P in the IA32_MCG_CAP MSR. Thus far, this feature has not been implemented by any IA-32 processor. Because this feature has not been implemented yet, we cannot say whether it will be shared among logical processors or not.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;
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&lt;DIV align="left"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: green; FONT-FAMILY: Arial"&gt;&lt;FONT color="#330000"&gt;Regards,&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
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      <pubDate>Thu, 03 Feb 2005 03:22:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/IA32-CTL-Model-Specific-Register/m-p/939481#M16700</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2005-02-03T03:22:18Z</dc:date>
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