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    <title>topic Re: Kernel Registers in IPF in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944795#M18064</link>
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&lt;DIV&gt;&lt;FONT size="2"&gt;We're forwarding this question to our Application Engineering team. We'll let you know how they respond.&lt;/FONT&gt;&lt;/DIV&gt;
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    <pubDate>Fri, 13 Aug 2004 04:06:47 GMT</pubDate>
    <dc:creator>Intel_Software_Netw1</dc:creator>
    <dc:date>2004-08-13T04:06:47Z</dc:date>
    <item>
      <title>Kernel Registers in IPF</title>
      <link>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944794#M18063</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;The Itanium Architecture for Software Developers talks about the Kernel Registers. It states:&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;The eight kernel registers, labeled Kr0 through Kr7, are used to convey information from the operating system to the application program. For instance, the operating system can put read-only, semi-static information such as processor ID into one of the Kernel registers.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Question, If it is read only, how does the OS put information into the register? Is it read only to an application but not to the OS? I am not running under Windows or Linux or anything other OS. I am running in a standalone environment. Am I free to read and write these kernel registers as I see fit and be guaranteed that the compilers won't use them for "normal" code? I want some registers where I can put information that I MUST have extremely fast access to and a dedicated register would be perfect. How can I leverage these or any other register inside the Itanium and be guaranteed that the compilers won't allocate them for use behind my back?&lt;/DIV&gt;</description>
      <pubDate>Sat, 07 Aug 2004 05:52:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944794#M18063</guid>
      <dc:creator>awbeale</dc:creator>
      <dc:date>2004-08-07T05:52:13Z</dc:date>
    </item>
    <item>
      <title>Re: Kernel Registers in IPF</title>
      <link>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944795#M18064</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
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&lt;DIV&gt;&lt;FONT size="2"&gt;We're forwarding this question to our Application Engineering team. We'll let you know how they respond.&lt;/FONT&gt;&lt;/DIV&gt;
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      <pubDate>Fri, 13 Aug 2004 04:06:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944795#M18064</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2004-08-13T04:06:47Z</dc:date>
    </item>
    <item>
      <title>Re: Kernel Registers in IPF</title>
      <link>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944796#M18065</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;Here is the response we received from our Application Engineers:&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;FONT color="#006600" size="2"&gt;The phrasing of the paragraph in the Itanium Architecture Manual is not completely clear, but the essence is that the data that the OS places there is read-only for all user-level processes. The OS (because it runs at ring 0) has the necessary privileges to write to these registers. That is not clear in this paragraph. Volume 3 of the Software Developer's Manual (SDM) clearly explains how to use the special instructions that reference these registers and what privilege levels are required.&lt;BR /&gt;&lt;BR /&gt;KR0 through KR7 are kernel registers, but kernel registers are a subset of the Application Registers. You read and write them using the "Move Application Register" Instruction. If you look at the instruction "Move Application Register" in Volume 3 of the SDM, the pseudo code shows that when you move data to (write) a Kernel Register, you must be at Privilege Level 0. Otherwise the instruction will be interrupted with a Privileged Register Fault. This protection mechanism makes these registers Read/Write for the Operating System code at Privilege Level 0, but Read-Only for Application code at Privilege Level 3.&lt;BR /&gt;&lt;BR /&gt;In this fashion, applications (user level processes) cannot write to the kernel registers, but the OS can, placing semi-static information such as processor ID for use by user-level processes. The user-level processes can freely read these registers with the appropriate "Move Application Register" instruction in order to quickly reference the data that they hold without having to execute a system-level call.&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;DIV&gt;&lt;FONT size="2"&gt;We hope this is helpful.&lt;/FONT&gt;&lt;/DIV&gt;
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&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;
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      <pubDate>Fri, 13 Aug 2004 06:07:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944796#M18065</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2004-08-13T06:07:28Z</dc:date>
    </item>
    <item>
      <title>Re: Kernel Registers in IPF</title>
      <link>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944797#M18066</link>
      <description>&lt;DIV&gt;Thank you very much! Worked great! I am now accessing the kernel registers for my critical state! Thank you again!&lt;/DIV&gt;</description>
      <pubDate>Fri, 13 Aug 2004 22:41:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Kernel-Registers-in-IPF/m-p/944797#M18066</guid>
      <dc:creator>awbeale</dc:creator>
      <dc:date>2004-08-13T22:41:37Z</dc:date>
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