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    <title>topic performance of SCIF RMA in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950013#M19271</link>
    <description>&lt;P&gt;I tried to use SCIF RMA to exchange a large amount of data between two MICs but find it's almost impossible to align memory address of both card to 4K page.&lt;/P&gt;

&lt;P&gt;Using memory exchange through host gives me 1.7 speed up over single card. How much more performance&amp;nbsp;would SCIF RMA give if I can get it work? I want to decide if I should continue working in this direction.&lt;/P&gt;

&lt;P&gt;Thanks a lot.&lt;/P&gt;</description>
    <pubDate>Mon, 06 Jan 2014 04:44:48 GMT</pubDate>
    <dc:creator>Jun_Z_2</dc:creator>
    <dc:date>2014-01-06T04:44:48Z</dc:date>
    <item>
      <title>performance of SCIF RMA</title>
      <link>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950013#M19271</link>
      <description>&lt;P&gt;I tried to use SCIF RMA to exchange a large amount of data between two MICs but find it's almost impossible to align memory address of both card to 4K page.&lt;/P&gt;

&lt;P&gt;Using memory exchange through host gives me 1.7 speed up over single card. How much more performance&amp;nbsp;would SCIF RMA give if I can get it work? I want to decide if I should continue working in this direction.&lt;/P&gt;

&lt;P&gt;Thanks a lot.&lt;/P&gt;</description>
      <pubDate>Mon, 06 Jan 2014 04:44:48 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950013#M19271</guid>
      <dc:creator>Jun_Z_2</dc:creator>
      <dc:date>2014-01-06T04:44:48Z</dc:date>
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    <item>
      <title>Hi Jun,</title>
      <link>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950014#M19272</link>
      <description>&lt;P&gt;Hi Jun,&lt;/P&gt;

&lt;P&gt;A recent paper, posted at &lt;A href="http://software.intel.com/en-us/forums/topic/507126"&gt;http://software.intel.com/en-us/forums/topic/507126&lt;/A&gt;&amp;nbsp;, discussed about scif0 virtual Infiniband adapter. Hope this helps.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 02 Apr 2014 18:18:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950014#M19272</guid>
      <dc:creator>Loc_N_Intel</dc:creator>
      <dc:date>2014-04-02T18:18:04Z</dc:date>
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    <item>
      <title>Quote:Jun Z. wrote:</title>
      <link>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950015#M19273</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Jun Z. wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;it's almost impossible to align memory address of both card to 4K page.&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;You don't need to align SCIF transfers to page boundaries (4KB)--only cacheline (64B) boundaries. (Technically, you can transfer between arbitrary byte ranges using the SCIF API; it's just that a slow software fallback is used for the part(s) of the transfer where source and destination are not both cacheline aligned. In the worst case, that would be the entire transfer.)&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Jun Z. wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Using memory exchange through host gives me 1.7 speed up over single card. How much more performance&amp;nbsp;would SCIF RMA give if I can get it work?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;When you say "memory exchange through host", what do you mean, and what exactly are you comparing it to? SCIF&amp;nbsp;&lt;/SPAN&gt;achieves&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&amp;nbsp;&amp;gt;6GB/s&amp;nbsp;&lt;/SPAN&gt;for large transfers&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;between host and card on the system configuration discussed in &lt;A href="http://www.intel.com/content/dam/www/public/us/en/documents/performance-briefs/xeon-phi-product-family-performance-brief.pdf"&gt;http://www.intel.com/content/dam/www/public/us/en/documents/performance-briefs/xeon-phi-product-family-performance-brief.pdf&lt;/A&gt;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;; the possible transfer rate between two cards depends on the system chipset, but I would not expect it to be separated from the host/card rate by a factor so large as 1.7....&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 02 Apr 2014 21:38:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/performance-of-SCIF-RMA/m-p/950015#M19273</guid>
      <dc:creator>Evan_P_Intel</dc:creator>
      <dc:date>2014-04-02T21:38:00Z</dc:date>
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