<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Intel(R) Data Plane in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Is-Xeon-phi-good-for-packet-processing/m-p/953025#M20069</link>
    <description>&lt;P&gt;Intel(R) Data Plane Development Kit (DPDK) has been used mainly on Xeon processors to enhance packet processing performance. Not sure if it supports Xeon Phi(TM) coprocessor.&lt;/P&gt;
&lt;P&gt;Withoiut DPDK, L3 forwading for the 2.40 Ghz Intel Xeon processor E5645 on a native Linux stack is about 1 Mpps per core (64 byte packets), that is 64 Mbps.&amp;nbsp;If I assume the same performance on Intel(R) Xeon Phi(TM), then I can see the maximum traffic rate is about 3.8 Gbps. Thank you.&lt;/P&gt;</description>
    <pubDate>Thu, 01 Aug 2013 22:24:58 GMT</pubDate>
    <dc:creator>Loc_N_Intel</dc:creator>
    <dc:date>2013-08-01T22:24:58Z</dc:date>
    <item>
      <title>Is Xeon phi good for packet processing</title>
      <link>https://community.intel.com/t5/Software-Archive/Is-Xeon-phi-good-for-packet-processing/m-p/953024#M20068</link>
      <description>&lt;P&gt;I have two 10G NIC and would like to redirect all the traffic to the Xeon phi where some native multithreading application is running there.&lt;/P&gt;
&lt;P&gt;Does the existing Xeon phi protocol stack API supports such high traffic rate (20Gbps ~ 40Gbps)?&lt;/P&gt;
&lt;P&gt;On Xeon we could run DPDK. But I am not sure whether Xeon Phi can do something similar to handle high traffic rate and send back to the host.&lt;/P&gt;</description>
      <pubDate>Wed, 17 Jul 2013 18:57:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Is-Xeon-phi-good-for-packet-processing/m-p/953024#M20068</guid>
      <dc:creator>Leo_S_</dc:creator>
      <dc:date>2013-07-17T18:57:39Z</dc:date>
    </item>
    <item>
      <title>Intel(R) Data Plane</title>
      <link>https://community.intel.com/t5/Software-Archive/Is-Xeon-phi-good-for-packet-processing/m-p/953025#M20069</link>
      <description>&lt;P&gt;Intel(R) Data Plane Development Kit (DPDK) has been used mainly on Xeon processors to enhance packet processing performance. Not sure if it supports Xeon Phi(TM) coprocessor.&lt;/P&gt;
&lt;P&gt;Withoiut DPDK, L3 forwading for the 2.40 Ghz Intel Xeon processor E5645 on a native Linux stack is about 1 Mpps per core (64 byte packets), that is 64 Mbps.&amp;nbsp;If I assume the same performance on Intel(R) Xeon Phi(TM), then I can see the maximum traffic rate is about 3.8 Gbps. Thank you.&lt;/P&gt;</description>
      <pubDate>Thu, 01 Aug 2013 22:24:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Is-Xeon-phi-good-for-packet-processing/m-p/953025#M20069</guid>
      <dc:creator>Loc_N_Intel</dc:creator>
      <dc:date>2013-08-01T22:24:58Z</dc:date>
    </item>
  </channel>
</rss>

