<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic You can disable vectorization in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970258#M23737</link>
    <description>&lt;P&gt;You can disable vectorization on a per loop basis using !DIR$ NOVECTOR.&lt;/P&gt;
&lt;P&gt;You can provide the compiler with more information about the nature of an individual loop that you want vectorized using !DIR$ VECTOR [clause[,clause[,..]]] where clause can be things like&amp;nbsp;UNALIGNED to warn the compiler not to make assumptions about data alignment when vectorizing the loop. (This is one of the things that can cause memory addressing to go wrong inside a loop.)&lt;/P&gt;
&lt;P&gt;You can use !DIR$ ATTRIBUTES VECTOR [:clause] on an individual loop where clause can be things like NOMASK. You had asked what the k2 was for - it is a mask. The section of code you copied doesn't show k2 being set, so I don't know why it is 0.&lt;/P&gt;
&lt;P&gt;These directives have other options you can play around with but I would try the UNALIGNED and then the NOMASK first and finally the NOVECTOR if necessary.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Let me know what happens.&lt;/P&gt;</description>
    <pubDate>Tue, 28 May 2013 20:46:17 GMT</pubDate>
    <dc:creator>Frances_R_Intel</dc:creator>
    <dc:date>2013-05-28T20:46:17Z</dc:date>
    <item>
      <title>segfault in automatically vectorized code</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970249#M23728</link>
      <description>&lt;P&gt;&lt;/P&gt;
&lt;P&gt;I have a very baffling segfault in automatically vectorized code, perhaps someone have seen it before and can offer some suggestions..&lt;/P&gt;
&lt;P&gt;First of all, this is a plain C++ code, compiled with icpc using the following switches:&lt;/P&gt;
&lt;P&gt;-fopenmp -O3 -mmic -openmp -fma&amp;nbsp; -inline-debug-info -fp-model fast -DUSE_SSE=0 -DUSE_AVX=0 -DUSE_MIC=0 -DUSE_PFLOAT=1 -DUSE_RFLOAT=1 -DDEBUG=0&amp;nbsp; -mcmodel=medium -debug parallel &lt;/P&gt;
&lt;P&gt;If I drop -mmic the code runs fine on Xeon E5 processor. I can see the error also with -O2 and -O. The code executes for a while running the same instructions before the segfault occurs.&lt;/P&gt;
&lt;P&gt;If I run the code on Xeon Phi it crashes in similar looking pieces of C code. The time it crashes varies with the number of threads and compile settings. I have seen it crash when running single-threaded (but this takes a long time).&lt;/P&gt;
&lt;P&gt;C code:&lt;/P&gt;
&lt;P&gt;sum = 0.0;&lt;BR /&gt;cnt = 0;&lt;BR /&gt;&amp;nbsp;for(register int i = shift; i &amp;lt; K; i++){&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; if(outlier&lt;I&gt; || outlier[i-shift])&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; continue;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; register double y = Yfrag[i-shift];&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; register double x = Xfrag&lt;I&gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; register double vary = varF + var*(x+y);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; register double err = x-y;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; if(DEBUG) assert(vary &amp;gt; 0.0);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; sum += err*err/vary;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; cnt++;&lt;BR /&gt;}&lt;/I&gt;&lt;/I&gt;&lt;/P&gt;
&lt;P&gt;I have tried to remove register keyword thinking that this confuses the compiler, with no change in segfault.&lt;/P&gt;
&lt;P&gt;Using gdb, the crash occurs in assembler instruction corresponding to&lt;/P&gt;
&lt;P&gt;register double x = Xfrag&lt;I&gt;;&lt;/I&gt;&lt;/P&gt;
&lt;P&gt;the assembler dump from gdb is&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa54 &amp;lt;+42292&amp;gt;: movabs $0x63f680,%r13&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa5e &amp;lt;+42302&amp;gt;: vmovapd 0x8(%r11,%r14,1),%zmm30{%k3}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa69 &amp;lt;+42313&amp;gt;: kxnor&amp;nbsp; %k0,%k0&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa6d &amp;lt;+42317&amp;gt;: vgatherdpd 0x40(%rcx,%zmm24,8),%zmm31{%k5}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa75 &amp;lt;+42325&amp;gt;: jkzd&amp;nbsp;&amp;nbsp; 0x4cfa87 &amp;lt;Calign::IsRepeatRegion()+42343&amp;gt;,%k5&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa7a &amp;lt;+42330&amp;gt;: vgatherdpd 0x40(%rcx,%zmm24,8),%zmm31{%k5}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa82 &amp;lt;+42338&amp;gt;: jknzd&amp;nbsp; 0x4cfa6d &amp;lt;Calign::IsRepeatRegion()+42317&amp;gt;,%k5&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa87 &amp;lt;+42343&amp;gt;: vpxorq %zmm2,%zmm2,%zmm2&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa8d &amp;lt;+42349&amp;gt;: vaddpd %zmm30,%zmm29,%zmm11&lt;BR /&gt;=&amp;gt; 0x00000000004cfa93 &amp;lt;+42355&amp;gt;: vmovapd 0x48(%r11,%r14,1),%zmm2{%k2}&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfa9e &amp;lt;+42366&amp;gt;: vsubpd %zmm29,%zmm30,%zmm25&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfaa4 &amp;lt;+42372&amp;gt;: vaddpd %zmm2,%zmm31,%zmm3&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfaaa &amp;lt;+42378&amp;gt;: vpermf32x4 $0x0,%zmm27,%zmm1&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfab1 &amp;lt;+42385&amp;gt;: vpermf32x4 $0x0,%zmm28,%zmm12&lt;BR /&gt;&amp;nbsp;&amp;nbsp; 0x00000000004cfab8 &amp;lt;+42392&amp;gt;: vsubpd %zmm31,%zmm2,%zmm26&lt;/P&gt;
&lt;P&gt;A particular puzzle to me is what exactly causes a segfault. The register values are&lt;/P&gt;
&lt;P&gt;(gdb) print $r11&lt;BR /&gt;$1 = 0&lt;BR /&gt;(gdb) print $r14&lt;BR /&gt;$2 = 140726616854456&lt;BR /&gt;(gdb) print $zmm2&lt;BR /&gt;$3 = {v16_float = {0 &amp;lt;repeats 16 times&amp;gt;}, v8_double = {0, 0, 0, 0, 0, 0, 0, 0}, v64_int8 = {0 &amp;lt;repeats 64 times&amp;gt;}, v32_int16 = {0 &amp;lt;repeats 32 times&amp;gt;}, v16_int32 = {0 &amp;lt;repeats 16 times&amp;gt;}, v8_int64 = {0, 0, 0, &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0, 0, 0, 0, 0}, v4_uint128 = {0, 0, 0, 0}}&lt;BR /&gt;(gdb) print $k2&lt;BR /&gt;$4 = 0&lt;BR /&gt;(gdb) print ((double *)$r14)[0]&lt;BR /&gt;$5 = 5.4553999999999974&lt;BR /&gt;(gdb) print ((double *)$r14)[1]&lt;BR /&gt;$6 = 8.5977999999999781&lt;BR /&gt;(gdb) print ((double *)$r14)[8]&lt;BR /&gt;$7 = 0&lt;BR /&gt;(gdb) print ((double *)$r14)[9]&lt;BR /&gt;$8 = 0&lt;BR /&gt;(gdb) print ((double *)$r14)[10]&lt;BR /&gt;$9 = 0&lt;BR /&gt;(gdb) print ((double *)$r14)[16]&lt;BR /&gt;$10 = 0&lt;BR /&gt;(gdb) print ((double *)$r14)[17]&lt;BR /&gt;$11 = 0&lt;BR /&gt;(gdb) print ((double *)$r14)[20]&lt;BR /&gt;$12 = 0&lt;/P&gt;
&lt;P&gt;Which indicate the call should succeed. Is there any probably for vmovapd when the final address is aligned, but the value in the register is not aligned ? Also what is the meaning of k2=0 ?&lt;/P&gt;
&lt;P&gt;thank you very much&lt;/P&gt;
&lt;P&gt;Vladimir Dergachev&lt;/P&gt;
&lt;P&gt;PS This is Xeon Phi stepping B0, 8 GB RAM, passively cooled, the temperature never exceeded 70 degrees, plenty of unused RAM.&lt;/P&gt;</description>
      <pubDate>Thu, 23 May 2013 19:20:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970249#M23728</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-23T19:20:27Z</dc:date>
    </item>
    <item>
      <title>Update: adding -no-vec option</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970250#M23729</link>
      <description>&lt;P&gt;Update: adding -no-vec option produces code correctly working on Xeon Phi.&lt;/P&gt;
&lt;P&gt;Also, when the segfault occurs (with vectorization enabled) the linux kernel reports it as "error 4".&lt;/P&gt;</description>
      <pubDate>Thu, 23 May 2013 21:46:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970250#M23729</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-23T21:46:36Z</dc:date>
    </item>
    <item>
      <title>What is r11,r14 content</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970251#M23730</link>
      <description>&lt;P&gt;&lt;/P&gt;
&lt;P&gt;What is r11,r14 content during execution of this line of code &lt;STRONG&gt; 0x00000000004cfa5e &amp;lt;+42302&amp;gt;: vmovapd 0x8(%r11,%r14,1),%zmm30{%k3}&lt;/STRONG&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 24 May 2013 05:07:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970251#M23730</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-05-24T05:07:06Z</dc:date>
    </item>
    <item>
      <title>(gdb) print $r11$1 = 0(gdb)</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970252#M23731</link>
      <description>&lt;P&gt;(gdb) print $r11&lt;BR /&gt;$1 = 0&lt;BR /&gt;(gdb) print $r14&lt;BR /&gt;$2 = 140726616854456&lt;/P&gt;</description>
      <pubDate>Fri, 24 May 2013 16:06:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970252#M23731</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-24T16:06:39Z</dc:date>
    </item>
    <item>
      <title>If you can make a small</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970253#M23732</link>
      <description>&lt;P&gt;If you can make a small version of your program that demonstrates the problem, I will pass it on to the developers. I know this might not be an easy thing to do.&lt;/P&gt;</description>
      <pubDate>Fri, 24 May 2013 19:44:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970253#M23732</guid>
      <dc:creator>Frances_R_Intel</dc:creator>
      <dc:date>2013-05-24T19:44:43Z</dc:date>
    </item>
    <item>
      <title>I'll keep an eye on it. For</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970254#M23733</link>
      <description>&lt;P&gt;I'll keep an eye on it. For now I switched to using -no-vec and using #pragma simd in places which need optimization.&lt;/P&gt;
&lt;P&gt;The confusing issue is what exactly causes the segfault. Given that the the code runs for a while it is likely that just isolating the code with the segfault will not help.&lt;/P&gt;</description>
      <pubDate>Fri, 24 May 2013 21:51:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970254#M23733</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-24T21:51:16Z</dc:date>
    </item>
    <item>
      <title>-no-vec is a pretty big</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970255#M23734</link>
      <description>&lt;P&gt;-no-vec is a pretty big hammer to use as a work around. Have you tried simplifying the other options you are using on the command line? I don't know what all of your defines are for (seeing "&amp;nbsp;-DUSE_SSE=0 -DUSE_AVX=0 -DUSE_MIC=0" all on the same compile line does seem strange to me) but as far as the Intel compiler options, have you tried limiting them to just "-openmp -mmic"?&lt;/P&gt;</description>
      <pubDate>Fri, 24 May 2013 23:01:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970255#M23734</guid>
      <dc:creator>Frances_R_Intel</dc:creator>
      <dc:date>2013-05-24T23:01:08Z</dc:date>
    </item>
    <item>
      <title>Quote:Frances Roth (Intel)</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970256#M23735</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Frances Roth (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;-no-vec is a pretty big hammer to use as a work around. Have you tried simplifying the other options you are using on the command line? I don't know what all of your defines are for (seeing "&amp;nbsp;-DUSE_SSE=0 -DUSE_AVX=0 -DUSE_MIC=0" all on the same compile line does seem strange to me) but as far as the Intel compiler options, have you tried limiting them to just "-openmp -mmic"?&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;The defines are just to turn on and off sections of hand-coded intrinsics in our code.&lt;/P&gt;
&lt;P&gt;Yes, I tried running with just -mmic -openmp, same thing.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 25 May 2013 00:02:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970256#M23735</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-25T00:02:57Z</dc:date>
    </item>
    <item>
      <title>Are there any more fine</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970257#M23736</link>
      <description>&lt;P&gt;Are there any more fine-grained ways to limit automatic vectorization besides -no-vec ? Maybe this will shed some light on the problem..&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 25 May 2013 00:28:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970257#M23736</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-25T00:28:18Z</dc:date>
    </item>
    <item>
      <title>You can disable vectorization</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970258#M23737</link>
      <description>&lt;P&gt;You can disable vectorization on a per loop basis using !DIR$ NOVECTOR.&lt;/P&gt;
&lt;P&gt;You can provide the compiler with more information about the nature of an individual loop that you want vectorized using !DIR$ VECTOR [clause[,clause[,..]]] where clause can be things like&amp;nbsp;UNALIGNED to warn the compiler not to make assumptions about data alignment when vectorizing the loop. (This is one of the things that can cause memory addressing to go wrong inside a loop.)&lt;/P&gt;
&lt;P&gt;You can use !DIR$ ATTRIBUTES VECTOR [:clause] on an individual loop where clause can be things like NOMASK. You had asked what the k2 was for - it is a mask. The section of code you copied doesn't show k2 being set, so I don't know why it is 0.&lt;/P&gt;
&lt;P&gt;These directives have other options you can play around with but I would try the UNALIGNED and then the NOMASK first and finally the NOVECTOR if necessary.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Let me know what happens.&lt;/P&gt;</description>
      <pubDate>Tue, 28 May 2013 20:46:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970258#M23737</guid>
      <dc:creator>Frances_R_Intel</dc:creator>
      <dc:date>2013-05-28T20:46:17Z</dc:date>
    </item>
    <item>
      <title>Great, thanks !</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970259#M23738</link>
      <description>&lt;P&gt;Great, thanks !&lt;/P&gt;
&lt;P&gt;#pragma vector unaligned sprinkled in the function where segfault happens fixed the problem. I wonder whether this has something to do with the function being a member of C++ class - most of our other functions are plain C. &lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2013 00:02:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970259#M23738</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-29T00:02:09Z</dc:date>
    </item>
    <item>
      <title>My apologies for answering</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970260#M23739</link>
      <description>&lt;P&gt;My apologies for answering you in Fortran; I'm glad you were able to translate it into C/C++. Fortran is my native language and sometimes I slip up. And yes, it might have something to do which the function being part of a C++ class. But, as I said, my native language is Fortran. So I will leave it to other to expand on that subject.&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2013 03:14:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970260#M23739</guid>
      <dc:creator>Frances_R_Intel</dc:creator>
      <dc:date>2013-05-29T03:14:14Z</dc:date>
    </item>
    <item>
      <title>Sorry for late answer.I see</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970261#M23740</link>
      <description>&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Sorry for late answer.I see that the problem was resolved.&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2013 09:18:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970261#M23740</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-05-29T09:18:18Z</dc:date>
    </item>
    <item>
      <title>Fortran has its advantages ;)</title>
      <link>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970262#M23741</link>
      <description>&lt;P&gt;Fortran has its advantages ;)&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2013 15:51:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/segfault-in-automatically-vectorized-code/m-p/970262#M23741</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-05-29T15:51:27Z</dc:date>
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  </channel>
</rss>

