<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Trace cache and self-modifying code in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971227#M23990</link>
    <description>&lt;DIV&gt;&lt;FONT size="2"&gt;
&lt;P&gt;IA-32 Software Developer's Manual says:&lt;/P&gt;
&lt;P&gt;For the Pentium 4 and Intel Xeon processors, a write or a snoop of an instruction in a code segment, where the target instruction is already decoded and resident in the trace cache, invalidates the entire trace cache.&lt;/P&gt;
&lt;P&gt;Does every executed instruction get into the trace cache? If an instruction, which was executed only once but very recently, is modified, will that invalidate the trace cache?&lt;/P&gt;
&lt;P&gt;Does this also mean that if code is read as data, the trace cache can be invalidated?&lt;/P&gt;
&lt;P&gt;Are algorithms used by trace cache in Intel's processors described anywhere?&lt;/P&gt;
&lt;P&gt;Thanks&lt;/P&gt;&lt;/FONT&gt;&lt;/DIV&gt;</description>
    <pubDate>Fri, 07 Oct 2005 14:46:47 GMT</pubDate>
    <dc:creator>dm71</dc:creator>
    <dc:date>2005-10-07T14:46:47Z</dc:date>
    <item>
      <title>Trace cache and self-modifying code</title>
      <link>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971227#M23990</link>
      <description>&lt;DIV&gt;&lt;FONT size="2"&gt;
&lt;P&gt;IA-32 Software Developer's Manual says:&lt;/P&gt;
&lt;P&gt;For the Pentium 4 and Intel Xeon processors, a write or a snoop of an instruction in a code segment, where the target instruction is already decoded and resident in the trace cache, invalidates the entire trace cache.&lt;/P&gt;
&lt;P&gt;Does every executed instruction get into the trace cache? If an instruction, which was executed only once but very recently, is modified, will that invalidate the trace cache?&lt;/P&gt;
&lt;P&gt;Does this also mean that if code is read as data, the trace cache can be invalidated?&lt;/P&gt;
&lt;P&gt;Are algorithms used by trace cache in Intel's processors described anywhere?&lt;/P&gt;
&lt;P&gt;Thanks&lt;/P&gt;&lt;/FONT&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 07 Oct 2005 14:46:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971227#M23990</guid>
      <dc:creator>dm71</dc:creator>
      <dc:date>2005-10-07T14:46:47Z</dc:date>
    </item>
    <item>
      <title>Re: Trace cache and self-modifying code</title>
      <link>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971228#M23991</link>
      <description>&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Greetings from Intel Software Network Support. We are forwarding your question to our engineering contacts, and will let you know how they respond.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Lexi S.&lt;BR /&gt;Intel Software Network Support&lt;BR /&gt;&lt;/FONT&gt;&lt;A href="http://www.intel.com/software/" target="_blank"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/A&gt;&lt;A href="http://www.intel.com/software/" target="_blank"&gt;http://www.intel.com/software/&lt;/A&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;email: &lt;/FONT&gt;&lt;A href="mailto:ISN.support@intel.com" target="_blank"&gt;&lt;FONT size="2"&gt;ISN.support@intel.com&lt;/FONT&gt;&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;*Other names and brands may be claimed as the property of others.&lt;/FONT&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 07 Oct 2005 23:08:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971228#M23991</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2005-10-07T23:08:22Z</dc:date>
    </item>
    <item>
      <title>Re: Trace cache and self-modifying code</title>
      <link>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971229#M23992</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Greetings from Intel Software Network Support. You are asking for details that may be covered under NDA. Feel free to send yourquestion directly to Intel Software NetworkSupportthrough the support linklisted below, and we will be sure to get you a timely answer to your questions.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;If your company wishes toenroll for membership in the Intel Software Network'sEarly Access Program, you may go to the Early Access Program page at &lt;A href="http://intel.com/cd/ids/developer/asmo-na/eng/eap/19383.htm" target="_blank"&gt;http://intel.com/cd/ids/developer/asmo-na/eng/eap/19383.htm&lt;/A&gt;and apply on-line.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;I hope thiswill giveyou the information that you seek.&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Best regards,&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;Jim A.&lt;BR /&gt;Intel Software Network Support&lt;BR /&gt;&lt;/FONT&gt;&lt;A href="http://www.intel.com/software/" target="_blank"&gt;&lt;FONT color="#000000" size="2"&gt;&lt;/FONT&gt;&lt;/A&gt;&lt;A href="http://www.intel.com/software/" target="_blank"&gt;http://www.intel.com/software/&lt;/A&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;&lt;A href="http://www.intel.com/cd/ids/developer/asmo-na/eng/58987.htm" target="_blank"&gt;Contact us&lt;/A&gt;&lt;/FONT&gt;&lt;/DIV&gt;
&lt;DIV align="left"&gt;&lt;FONT size="2"&gt;*Other names and brands may be claimed as the property of others.&lt;/FONT&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by intel.software.network.support on &lt;SPAN class="date_text"&gt;11-15-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;11:09 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 12 Oct 2005 06:53:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Trace-cache-and-self-modifying-code/m-p/971229#M23992</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2005-10-12T06:53:52Z</dc:date>
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  </channel>
</rss>

