topic lea behaviour in Software Archive

lea behaviour

Vladimir_Dergachev — Sat, 25 May 2013 00:33:22 GMT

What are the sideeffects of LEA instruction ?

I am seeing a fairly large number of CPU cycles attributed to LEA, which is used to compute &ARRAY[base+i*stride+j]. Does the computed address cause a cache fault ?

thank you

Vladimir Dergachev

lea cannot cause a cache miss

James_C_Intel2 — Tue, 28 May 2013 07:16:46 GMT

lea cannot cause a cache miss, because it does not perform a memory access. It is just doing arithmetic on registers. If you are seeing a lot of time attributed to lea operations, then it is probably caused by dependency stalls in the in-order pipe (so cases where the lea is using as input a register whose value was modified in the previous instruction).

Ahh, thank you ! I was not

Vladimir_Dergachev — Tue, 28 May 2013 15:47:52 GMT

Ahh, thank you ! I was not sure how much of mov functionality was retained. Is the latency information available anywhere ? I'd like to understand where the stalls are coming from - in some cases lea had a lot of time attributed to it, even though neighbouring instructions with similar dependency levels had much lower time.

Could this be due to difficulty sharing lea hardware between four threads ?

The best tool to identify

TaylorIoTKidd — Mon, 26 Aug 2013 20:13:57 GMT

The best tool to identify such stalls is VTune (http://software.intel.com/en-us/intel-vtune-amplifier-xe) or a simliar tool.

Regards
--
Taylor