https://community.intel.com/t5/Software-Archive/forwarding-technique/m-p/976071#M25019 <P>The Intel Xeon Phi coprocessor vector micorarchitecture does use forwarding. You can read more about the microarchitecture in the following article.&nbsp;</P> <P><A href="http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-vector-microarchitecture">http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-vector-microarchitecture</A></P> Wed, 21 Aug 2013 17:26:36 GMT Sumedh_N_Intel 2013-08-21T17:26:36Z https://community.intel.com/t5/Software-Archive/forwarding-technique/m-p/976070#M25018 <P>Hi, I have a question on the pipeline of Xeon Phi. That is, does the pipeline of Xeon Phi support forwarding technique? If it does, there should not be any stalls for the RAW instructions (suppose the instructions access register only and no memory access).&nbsp;</P> <P>(1) ADD <STRONG>R1</STRONG>, R2, R3 &nbsp; &nbsp;// write the result into register R1</P> <P>(2) MUL R5, <STRONG>R1,</STRONG> R4 &nbsp; &nbsp;// read the content of register R1</P> <P>In theory, if the pipeline suupports the forwarding technique, there should not be any stalls between instruction (1) and instruction (2).</P> <P></P> <P>Jianbin</P> Wed, 14 Aug 2013 15:10:47 GMT https://community.intel.com/t5/Software-Archive/forwarding-technique/m-p/976070#M25018 Jianbin_F_ 2013-08-14T15:10:47Z https://community.intel.com/t5/Software-Archive/forwarding-technique/m-p/976071#M25019 <P>The Intel Xeon Phi coprocessor vector micorarchitecture does use forwarding. You can read more about the microarchitecture in the following article.&nbsp;</P> <P><A href="http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-vector-microarchitecture">http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-vector-microarchitecture</A></P> Wed, 21 Aug 2013 17:26:36 GMT https://community.intel.com/t5/Software-Archive/forwarding-technique/m-p/976071#M25019 Sumedh_N_Intel 2013-08-21T17:26:36Z