topic I don't know what Intel means in Software Archive

raw latency

Jianbin_F_ — Thu, 15 Aug 2013 07:40:05 GMT

Hi,

In the SDG of Xeon Phi, it says the access time of L1 and L2 cache in terms of 'raw latency'. It is 1 cycle for the L1 cache and 11 cycles for the L2 cache. I wonder what does the 'raw latency' mean? And what's the difference from the 'real latency' seen by us programmers?

Jianbin

I don't know what Intel means

McCalpinJohn — Thu, 15 Aug 2013 20:43:55 GMT

I don't know what Intel means by "raw latency" for L2 accesses, but I have measured L2 cache hit latency at about 25 cycles using a couple of different techniques.

The commonly accepted meaning

Sumedh_N_Intel — Wed, 21 Aug 2013 19:36:44 GMT

The commonly accepted meaning of raw latency is the ideal latency for accessing the data in a single cache line. Real measurements often include other factors that will add to the ideal latency.