<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic This is what I found in the in Software Archive</title>
    <link>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978951#M25618</link>
    <description>&lt;P&gt;This is what I found in the Intel Xeon Phi coprocessor Instruction Set Architecture reference:&amp;nbsp;&lt;/P&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;Writes to overlapping destination memory locations are guaranteed to be ordered with&amp;nbsp;respect to each other (from LSB to MSB of the source registers). Only writes to overlapping&amp;nbsp;vector indices are guaranteed to be ordered with respect to each other (from LSB to MSB&amp;nbsp;of the source registers). Writes that are not overlapped may happen in any order. Memory&amp;nbsp;ordering with other instructions follows the Intel-64 memory ordering model. Note that&amp;nbsp;this does not account for non-overlapping indices that map into the same physical address&amp;nbsp;locations&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;From this, I deduce that same indices are allowed in a scatter instruction. Also, since the overlapping writes are ordered from LSB to MSB of the souce elements, I would expect the MSB value to be actually present in the memory location after the scatter has been executed.&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 11 Jun 2013 21:16:58 GMT</pubDate>
    <dc:creator>Sumedh_N_Intel</dc:creator>
    <dc:date>2013-06-11T21:16:58Z</dc:date>
    <item>
      <title>Scatter behaviour</title>
      <link>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978950#M25617</link>
      <description>&lt;P&gt;What does scatter instruction do when the indices are all the same (0 for example) ? Is this allowed, an if so which element actually gets stored ?&lt;/P&gt;
&lt;P&gt;Thank you !&lt;/P&gt;
&lt;P&gt;Vladimir Dergachev&lt;/P&gt;</description>
      <pubDate>Mon, 03 Jun 2013 16:13:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978950#M25617</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-06-03T16:13:56Z</dc:date>
    </item>
    <item>
      <title>This is what I found in the</title>
      <link>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978951#M25618</link>
      <description>&lt;P&gt;This is what I found in the Intel Xeon Phi coprocessor Instruction Set Architecture reference:&amp;nbsp;&lt;/P&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;Writes to overlapping destination memory locations are guaranteed to be ordered with&amp;nbsp;respect to each other (from LSB to MSB of the source registers). Only writes to overlapping&amp;nbsp;vector indices are guaranteed to be ordered with respect to each other (from LSB to MSB&amp;nbsp;of the source registers). Writes that are not overlapped may happen in any order. Memory&amp;nbsp;ordering with other instructions follows the Intel-64 memory ordering model. Note that&amp;nbsp;this does not account for non-overlapping indices that map into the same physical address&amp;nbsp;locations&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;From this, I deduce that same indices are allowed in a scatter instruction. Also, since the overlapping writes are ordered from LSB to MSB of the souce elements, I would expect the MSB value to be actually present in the memory location after the scatter has been executed.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 11 Jun 2013 21:16:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978951#M25618</guid>
      <dc:creator>Sumedh_N_Intel</dc:creator>
      <dc:date>2013-06-11T21:16:58Z</dc:date>
    </item>
    <item>
      <title>Excellent, this is exactly</title>
      <link>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978952#M25619</link>
      <description>&lt;P&gt;Excellent, this is exactly what I was looking for !&lt;/P&gt;
&lt;P&gt;Thank you very much,&lt;/P&gt;
&lt;P&gt;Vladimir Dergachev&lt;/P&gt;</description>
      <pubDate>Tue, 11 Jun 2013 21:24:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Archive/Scatter-behaviour/m-p/978952#M25619</guid>
      <dc:creator>Vladimir_Dergachev</dc:creator>
      <dc:date>2013-06-11T21:24:28Z</dc:date>
    </item>
  </channel>
</rss>

